公开(公告)号：US08987773B2

公开(公告)日：2015-03-24

申请号：US14027167

申请日：2013-09-14

Applicant: Samsung Display Co., Ltd.

Inventor： Hae-Yeon Lee ,  Jin-Gon Oh ,  Jung-Bae Kim ,  Jong-Hyun Choi ,  Keum-Nam Kim

IPC: H01L33/00 ,  H01L27/32

CPC classification number: H01L27/3279 ,  H01L27/3276

Abstract: An organic light emitting diode display includes: a pixel region; and a peripheral region surrounding the pixel region, the peripheral region including: a gate common voltage line; an interlayer insulating film that covers the gate common voltage line and has a common voltage contact hole exposing part of the gate common voltage line; a data common voltage line that is formed on the interlayer insulating film and comes in contact with the gate common voltage line via the common voltage contact hole; barrier ribs that cover the data common voltage line and have common voltage openings exposing part of the data common voltage line; and a peripheral common electrode that is formed on the barrier ribs and comes in contact with the data common voltage line via the common voltage openings, wherein the barrier ribs are formed at positions corresponding to the boundaries with the common voltage contact hole.

Abstract translation: 有机发光二极管显示器包括：像素区域; 以及围绕所述像素区域的周边区域，所述周边区域包括：栅极公共电压线; 覆盖所述栅极公共电压线并且具有暴露所述栅极公共电压线的一部分的公共电压接触孔的层间绝缘膜; 形成在层间绝缘膜上并通过公共电压接触孔与栅极公共电压线接触的数据公共电压线; 阻挡肋覆盖数据公共电压线，并具有暴露部分数据公共电压线的公共电压开口; 以及形成在隔壁上并通过公共电压开口与数据公共电压线接触的外围公共电极，其中在与公共电压接触孔的边界相对应的位置处形成阻挡肋。

公开(公告)号：US09659525B2

公开(公告)日：2017-05-23

申请号：US14737883

申请日：2015-06-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hai-Jung In ,  Dong-Gyu Kim ,  Jung-Bae Kim ,  Yong-Sung Park ,  Bo-Yong Chung

IPC: G09G5/00 ,  G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/00

Abstract: A display device includes a display panel, a data driver, a scan driver, and a power supply. The display panel includes power voltage lines and pixels coupled to data lines and scan lines. The data driver supplies data voltages to the data lines. The scan driver provides scan signals to the scan lines. The power supply supplies a power voltage to the power voltage lines. The display panel includes a compensation resistance coupled between s pixels and one of the power voltage lines.

公开(公告)号：US09041704B2

公开(公告)日：2015-05-26

申请号：US14040522

申请日：2013-09-27

Applicant: Samsung Display Co., Ltd.

Inventor： Hae-Yeon Lee ,  Bo-Yong Chung ,  Yong-Jae Kim ,  Jung-Bae Kim

IPC: G09G3/32 ,  H01L27/32

CPC classification number: H01L27/3262 ,  G09G3/325 ,  G09G3/3291 ,  G09G2300/0465 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/08

Abstract: A pixel circuit for an organic light emitting diode (OLED) display is disclosed. One inventive aspect includes an organic light emitting diode, a first transistor, a second transistor, a first capacitor connected to a second node and a fixed voltage source, a third transistor, a fourth transistor, a second capacitor connected to the fourth transistor and a third node, a first control transistor and a second control transistor. The fourth transistor is connected to the first and third nodes and is turned off when an emission control signal is supplied to an emission control line and turned on otherwise. The first control transistor is connected to the third node and the first power source and is turned on when a first control signal is supplied.

Abstract translation: 公开了一种用于有机发光二极管（OLED）显示器的像素电路。 一个创造性方面包括有机发光二极管，第一晶体管，第二晶体管，连接到第二节点的第一电容器和固定电压源，第三晶体管，第四晶体管，连接到第四晶体管的第二电容器和 第三节点，第一控制晶体管和第二控制晶体管。 第四晶体管连接到第一和第三节点，并且当发射控制信号被提供给发射控制线并且否则接通时，它被关断。 第一控制晶体管连接到第三节点和第一电源，并且当提供第一控制信号时被接通。

公开(公告)号：US12288823B2

公开(公告)日：2025-04-29

申请号：US18501614

申请日：2023-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jung-Bae Kim

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

公开(公告)号：US10032933B2

公开(公告)日：2018-07-24

申请号：US15622680

申请日：2017-06-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung-Bae Kim

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/02

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

公开(公告)号：US09147719B2

公开(公告)日：2015-09-29

申请号：US14231263

申请日：2014-03-31

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung-Bae Kim ,  Dong-Kyu Kim ,  Bo-Yong Chung

IPC: H01L35/24 ,  H01L27/32

CPC classification number: H01L27/326 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/3262 ,  H01L27/3276

Abstract: A thin film transistor array substrate includes: a substrate; a bottom gate electrode including a gate area doped with ion impurities and undoped areas on left and right sides of the gate area; an active layer on the bottom gate electrode with a first insulating layer therebetween and including a source contact region, a drain contact region, and an oxide semiconductor region; a top gate electrode on the active layer with a second insulating layer therebetween; and a source electrode in contact with the source contact region and a drain electrode in contact with the drain contact region, the source electrode and the drain electrode being on the top gate electrode with a third insulating layer therebetween. The oxide semiconductor region is between the source contact region and the drain contact region.

Abstract translation: 薄膜晶体管阵列基板包括：基板; 底栅电极，其包括掺杂有离子杂质的栅极区域和在栅极区域的左侧和右侧的未掺杂区域; 底栅电极上的有源层，其间具有第一绝缘层，并且包括源极接触区域，漏极接触区域和氧化物半导体区域; 有源层上的顶栅电极，其间具有第二绝缘层; 以及与所述源极接触区域接触的源极电极和与所述漏极接触区域接触的漏极电极，所述源极电极和所述漏极电极位于所述顶部栅极电极上，在其间具有第三绝缘层。 氧化物半导体区域在源极接触区域和漏极接触区域之间。

公开(公告)号：US09117708B2

公开(公告)日：2015-08-25

申请号：US14330859

申请日：2014-07-14

Applicant: Samsung Display Co., Ltd.

Inventor： Jung-Bae Kim ,  Bo-Yong Chung ,  Hae-Yeon Lee ,  Yong-Jae Kim

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/786 ,  H01L21/16 ,  H01L21/00

CPC classification number: H01L27/1255 ,  H01L21/00 ,  H01L21/16 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor includes a substrate, a gate electrode, a buffer layer, a gate insulating layer, an active layer, an etching stop layer, a source electrode and a drain electrode. The gate electrode is formed on the substrate. The buffer layer partially covers both side portions of the gate electrode. The gate insulating layer covers the gate electrode and the buffer layer. The active layer is formed on the gate insulating layer. The etching stop layer is formed on the active layer, and has a first opening and a second opening on the active layer. The source electrode is formed on the etching stop layer, and contacts with the active layer through the first opening. The drain electrode is formed on the etching stop layer, and is contacted with the active layer through the second opening.

Abstract translation: 薄膜晶体管包括基板，栅电极，缓冲层，栅极绝缘层，有源层，蚀刻停止层，源电极和漏电极。 栅电极形成在基板上。 缓冲层部分地覆盖栅电极的两侧部分。 栅极绝缘层覆盖栅电极和缓冲层。 有源层形成在栅绝缘层上。 蚀刻停止层形成在有源层上，并且在有源层上具有第一开口和第二开口。 源电极形成在蚀刻停止层上，并通过第一开口与有源层接触。 漏电极形成在蚀刻停止层上，并通过第二开口与有源层接触。

公开(公告)号：US20140077173A1

公开(公告)日：2014-03-20

申请号：US13797670

申请日：2013-03-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung-Bae Kim ,  Yong-Sung Park ,  Wang-Jo Lee ,  Hae-Yeon Lee ,  Keum-Nam Kim

IPC: H01L51/52 ,  H01L29/786

CPC classification number: H01L51/52 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/786

Abstract: A thin film transistor includes a substrate, a gate electrode on the substrate, an active layer spaced from the gate electrode, a source electrode and a drain electrode spaced from the gate electrode and coupled to the active layer, a gate wiring at a same layer as the gate electrode and coupled to the gate electrode, and first conductive members electrically coupled to, and overlapping, the gate wiring.

Abstract translation: 薄膜晶体管包括衬底，衬底上的栅电极，与栅极间隔开的有源层，与栅电极间隔开并耦合到有源层的源电极和漏极电极，位于相同层的栅极布线 作为栅极并且耦合到栅电极，以及第一导电构件，其电耦合到栅极布线并与栅极布线重叠。

公开(公告)号：US11843060B2

公开(公告)日：2023-12-12

申请号：US17360582

申请日：2021-06-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jung-Bae Kim

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78618 ,  H01L21/02565

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

公开(公告)号：US10403764B2

公开(公告)日：2019-09-03

申请号：US16042268

申请日：2018-07-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung-Bae Kim

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.