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    Display device
    1.
    发明授权
    Display device 有权

    公开(公告)号：US11984537B2

    公开(公告)日：2024-05-14

    申请号：US17188783

    申请日：2021-03-01

    Applicant: Samsung Display Co., Ltd.

    Inventor： Su Bin Bae ,  Yun Jong Yeo ,  Jung Yun Jo

    IPC: H01L33/38 ,  H01L33/40 ,  H01L33/42 ,  H01L33/50 ,  H01L33/62

    CPC classification number: H01L33/387 ,  H01L33/405 ,  H01L33/42 ,  H01L33/502 ,  H01L33/62

    Abstract: A display device includes a substrate; a first circuit part and a second circuit part on the substrate and spaced from each other in a first direction; and an emission part between the first circuit part and the second circuit part, the emission part being located between the first circuit part and the second circuit part in a direction parallel to the substrate, wherein the first circuit part includes a first electrode extending to the emission part, wherein the second circuit part includes a second electrode extending to the emission part, and wherein the emission part includes a light emitting element located between the first electrode and the second electrode.

    Display apparatus and manufacturing method thereof
    4.
    发明授权
    Display apparatus and manufacturing method thereof 有权

    公开(公告)号：US09691795B2

    公开(公告)日：2017-06-27

    申请号：US15175839

    申请日：2016-06-07

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jung Yun Jo ,  Su Bin Bae ,  Sang Hyeon Song ,  Cheol Geun An

    IPC: H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L27/12 ,  G06F3/041

    CPC classification number: H01L27/124 ,  G06F3/0416 ,  G06F2203/04103 ,  H01L27/1262

    Abstract: An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface.

    Connecting structure of a conductive layer
    5.
    发明授权
    Connecting structure of a conductive layer 有权

    公开(公告)号：US11276580B2

    公开(公告)日：2022-03-15

    申请号：US16296646

    申请日：2019-03-08

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Su Bin Bae ,  Yu-Gwang Jeong ,  Shin Il Choi ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L29/41 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L21/763

    Abstract: A connecting structure of a conductive layer includes a first conductive layer, a first insulating layer disposed on the first conductive layer and including a first opening overlapping the first conductive layer, a connecting conductor disposed on the first insulating layer and connected to the first conductive layer through the first opening, an insulator island disposed on the connecting conductor, a second insulating layer disposed on the first insulating layer and including a second opening overlapping the connecting conductor and the insulator island, and a second conductive layer disposed on the second insulating layer and connected to a connecting electrode through the second opening. A sum of a thickness of the first insulating layer and a thickness of the second insulating layer is greater than or equal to 1 μm, and each of the thicknesses of the first and second insulating layers is less than 1 μm.

    Transistor array panel and manufacturing method thereof
    7.
    发明授权
    Transistor array panel and manufacturing method thereof 有权

    公开(公告)号：US10741589B2

    公开(公告)日：2020-08-11

    申请号：US16215520

    申请日：2018-12-10

    Applicant: Samsung Display Co., Ltd.

    Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

    IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32

    Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

    Transistor array panel and manufacturing method thereof
    10.
    发明授权
    Transistor array panel and manufacturing method thereof 有权

    公开(公告)号：US11183518B2

    公开(公告)日：2021-11-23

    申请号：US16987952

    申请日：2020-08-07

    Applicant: Samsung Display Co., Ltd.

    Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

    IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32

    Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

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