公开(公告)号：US20240381732A1

公开(公告)日：2024-11-14

申请号：US18426382

申请日：2024-01-30

Applicant: Samsung Display Co., LTD.

Inventor： Min Uk KIM ,  Bo Hwa KIM ,  Che Ho LIM ,  Kang Uk KIM ,  Kwang Min LEE ,  Kang Soo HAN

IPC: H10K59/38 ,  H10K59/80

Abstract: A display device that includes a first substrate including a display area and a peripheral area disposed on a side of the display area, a second substrate disposed to face the first substrate, the second substrate including a first surface and a second surface, a pixel circuit layer disposed on the first substrate, a light emitting element disposed on the pixel circuit layer and in the display area, a color conversion layer disposed on the first surface of the second substrate, at least one bank pattern disposed on the first surface of the second substrate, a spacer disposed on the first surface of the second substrate, the spacer enclosed by the at least one bank pattern, a protective layer overlapping the color conversion layer, the at least one bank pattern, and the spacer, and a sealant overlapping at least a portion of the spacer.

公开(公告)号：US20240234580A9

公开(公告)日：2024-07-11

申请号：US18492927

申请日：2023-10-24

Applicant: Samsung Display Co., LTD.

Inventor： Sun Woo LEE ,  Jae Bum HAN ,  Bo Hwa KIM ,  Min Ji KIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

公开(公告)号：US20240170614A1

公开(公告)日：2024-05-23

申请号：US18459325

申请日：2023-08-31

Applicant: Samsung Display Co., LTD.

Inventor： Mi Hyang SHEEN ,  Dong Uk KIM ,  Kwan Jae LEE ,  Bo Hwa KIM ,  Dong Youn YOO ,  Hyeong Su CHOI

IPC: H01L33/38 ,  H01L25/075 ,  H01L33/24 ,  H01L33/50 ,  H01L33/62

CPC classification number: H01L33/382 ,  H01L25/0753 ,  H01L33/24 ,  H01L33/502 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0041

Abstract: A light-emitting element comprises a first semiconductor layer, an active layer provided on the first semiconductor layer, a second semiconductor layer provided on the active layer, an electrode layer provided on the second semiconductor layer, and an insulating film around outer peripheral surfaces of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer, wherein the active layer includes a cover layer including a plurality of quantum dots, and the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer are sequentially stacked in one direction to form a shape of a rod.

公开(公告)号：US20240136443A1

公开(公告)日：2024-04-25

申请号：US18492927

申请日：2023-10-23

Applicant: Samsung Display Co., LTD.

Inventor： Sun Woo LEE ,  Jae Bum HAN ,  Bo Hwa KIM ,  Min Ji KIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.