公开(公告)号：US20240234580A9

公开(公告)日：2024-07-11

申请号：US18492927

申请日：2023-10-24

Applicant: Samsung Display Co., LTD.

Inventor： Sun Woo LEE ,  Jae Bum HAN ,  Bo Hwa KIM ,  Min Ji KIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

公开(公告)号：US20240136443A1

公开(公告)日：2024-04-25

申请号：US18492927

申请日：2023-10-23

Applicant: Samsung Display Co., LTD.

Inventor： Sun Woo LEE ,  Jae Bum HAN ,  Bo Hwa KIM ,  Min Ji KIM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.