公开(公告)号：US11637562B2

公开(公告)日：2023-04-25

申请号：US17677511

申请日：2022-02-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto Modaffari ,  Paolo Pesenti ,  Germano Nicollini

IPC: H03M3/00 ,  H03M3/02

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

公开(公告)号：US11199422B2

公开(公告)日：2021-12-14

申请号：US17125599

申请日：2020-12-17

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Matteo Quartiroli ,  Alessandro Mecchia ,  Paolo Pesenti ,  Stefano Facchinetti ,  Andrea Donadel

IPC: G01C25/00 ,  G01C19/5776 ,  H04L27/22

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

公开(公告)号：US10900805B2

公开(公告)日：2021-01-26

申请号：US15919882

申请日：2018-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo Quartiroli ,  Alessandro Mecchia ,  Paolo Pesenti ,  Stefano Facchinetti ,  Andrea Donadel

IPC: G01C25/00 ,  G01C19/5776 ,  H04L27/22

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

公开(公告)号：US20210102822A1

公开(公告)日：2021-04-08

申请号：US17125599

申请日：2020-12-17

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Matteo Quartiroli ,  Alessandro Mecchia ,  Paolo Pesenti ,  Stefano Facchinetti ,  Andrea Donadel

IPC: G01C25/00 ,  G01C19/5776 ,  H04L27/22

Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.

公开(公告)号：US10648813B2

公开(公告)日：2020-05-12

申请号：US15919874

申请日：2018-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Mecchia ,  Matteo Quartiroli ,  Paolo Pesenti

IPC: G01C19/5776 ,  G01C19/5712 ,  H04L27/38 ,  B81B7/00

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

公开(公告)号：US11984860B2

公开(公告)日：2024-05-14

申请号：US17839335

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Modaffari ,  Paolo Pesenti ,  Mario Maiore ,  Tiziano Chiarillo

IPC: H03F3/70 ,  G01R27/26 ,  H03F3/45

CPC classification number: H03F3/70 ,  G01R27/2605 ,  H03F3/45968 ,  H03F2200/375

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

公开(公告)号：US10794772B2

公开(公告)日：2020-10-06

申请号：US15957999

申请日：2018-04-20

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Vaiana ,  Paolo Pesenti ,  Mario Chiricosta ,  Calogero Marco Ippolito ,  Mario Maiore

IPC: G01K3/14 ,  H03H17/02 ,  G01K7/02 ,  H03M3/00

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

公开(公告)号：US11740136B2

公开(公告)日：2023-08-29

申请号：US17011723

申请日：2020-09-03

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Vaiana ,  Paolo Pesenti ,  Mario Chiricosta ,  Calogero Marco Ippolito ,  Mario Maiore

IPC: G01K3/14 ,  H03H17/02 ,  G01K7/02 ,  H03M3/00 ,  H03K19/003 ,  H03K19/018

CPC classification number: G01K3/14 ,  G01K7/02 ,  G01K7/021 ,  H03H17/02 ,  G01K2219/00 ,  H03K19/00307 ,  H03K19/01825 ,  H03M3/43 ,  H03M3/456 ,  H03M3/458

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

公开(公告)号：US20180274924A1

公开(公告)日：2018-09-27

申请号：US15919874

申请日：2018-03-13

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Mecchia ,  Matteo Quartiroli ,  Paolo Pesenti

IPC: G01C19/5776 ,  G01C19/5712

CPC classification number: G01C19/5776 ,  B81B7/00 ,  B81B7/008 ,  B81B2201/0242 ,  G01C19/5712 ,  H04L27/3863

Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.

公开(公告)号：US12267078B2

公开(公告)日：2025-04-01

申请号：US18352581

申请日：2023-07-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Matteo Quartiroli ,  Alessandro Mecchia ,  Paolo Pesenti

IPC: H03L7/081 ,  H03L7/099

Abstract: A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.