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    Pre-Charge Technique For A Voltage Regulator
    1.
    发明申请
    Pre-Charge Technique For A Voltage Regulator 有权
    电压调节器的预充电技术

    公开(公告)号：US20160370816A1

    公开(公告)日：2016-12-22

    申请号：US14740386

    申请日：2015-06-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Dazhi Wei ,  Gang Yuan ,  Erik Pankratz ,  Imranul Islam ,  Praveen Kallam ,  Axel Thomsen ,  Kenneth Wilson Fernald ,  Jinwen Xiao

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/56 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

    Abstract translation: 在一个实施例中，一种装置包括用于控制电压调节器的控制器。 控制器可以具有第一比较器电路，以将第一参考电压与反馈电压进行比较。 反过来，第一比较器电路可以包括：第一比较器，具有用于接收反馈电压的第一输入端子和用于接收参考电压的第二输入端子和输出节点，以基于该比较来输出误差信号; 以及耦合在所述第一输入端子和所述输出节点之间的第一预充电电路，被配置为将补偿网络的第一部分预先充电到预充电电平。 第一控制器还可以包括耦合到第一比较器电路的第二比较器电路，将误差信号与斜坡信号进行比较，并产生第一控制输出，以在第一操作模式下控制电压调节器的传动系。

    System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods
    2.
    发明申请
    System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods 有权
    用于具有追赶模式和相关方法的时钟重新定时的系统和装置

    公开(公告)号：US20160119111A1

    公开(公告)日：2016-04-28

    申请号：US14523599

    申请日：2014-10-24

    Applicant: Silicon Laboratories Inc.

    Inventor： Kenneth W. Fernald ,  Imranul Islam

    IPC: H04L7/00

    CPC classification number: H04L7/0016 ,  H04L7/0338

    Abstract: An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal.

    Abstract translation: 一种装置包括响应于第一信号操作的模拟或混合信号电路，以及响应于第二信号操作的数字电路。 该装置还包括信号重新定时电路。 信号重新定时电路重置数字信号源的输出信号，以通过对数字信号源的输出信号的边沿进行重新定时以降低第一信号的周期边界来减小数字电路与模拟或混合信号电路之间的干扰。

    CLOCK SIGNAL TIMING-BASED NOISE SUPPRESSION
    3.
    发明申请
    CLOCK SIGNAL TIMING-BASED NOISE SUPPRESSION 有权
    基于时钟信号时序噪声抑制

    公开(公告)号：US20140266336A1

    公开(公告)日：2014-09-18

    申请号：US13832708

    申请日：2013-03-15

    Applicant: SILICON LABORATORIES INC.

    Inventor： Imranul Islam ,  Axen Thomsen ,  Paul I. Zavalney

    IPC: H03L7/06

    CPC classification number: H03L7/0816 ,  H03L7/0814

    Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

    Abstract translation: 一种方法包括从另一个时钟信号产生第一时钟信号和第二时钟信号中的一个。 第一时钟信号被配置为用于同步模拟系统的操作，并且第二时钟信号被配置为用于同步数字系统的操作。 该方法包括使用模拟系统的相位检测器来测量相对于第二时钟信号的第一时钟信号的定时; 并且该方法包括控制数字系统的延迟元件，以基于相位检测器的测量来调节定时，以抑制模拟系统中的噪声。

    Pre-charge technique for a voltage regulator
    4.
    发明授权
    Pre-charge technique for a voltage regulator 有权

    公开(公告)号：US09958888B2

    公开(公告)日：2018-05-01

    申请号：US14740386

    申请日：2015-06-16

    Applicant: Silicon Laboratories Inc.

    Inventor： Dazhi Wei ,  Gang Yuan ,  Erik Pankratz ,  Imranul Islam ,  Praveen Kallam ,  Axel Thomsen ,  Kenneth Wilson Fernald ,  Jinwen Xiao

    IPC: G05F1/575 ,  G05F1/56 ,  H02M3/158

    CPC classification number: G05F1/575 ,  G05F1/56 ,  H02M3/1588 ,  Y02B70/1466

    Abstract: In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.

    Clock signal timing-based noise suppression
    6.
    发明授权
    Clock signal timing-based noise suppression 有权
    时钟信号基于定时的噪声抑制

    公开(公告)号：US09083354B2

    公开(公告)日：2015-07-14

    申请号：US13832708

    申请日：2013-03-15

    Applicant: SILICON LABORATORIES INC.

    Inventor： Imranul Islam ,  Axel Thomsen ,  Paul I. Zavalney

    IPC: H03L7/06 ,  H03L7/081

    CPC classification number: H03L7/0816 ,  H03L7/0814

    Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

    Abstract translation: 一种方法包括从另一个时钟信号产生第一时钟信号和第二时钟信号中的一个。 第一时钟信号被配置为用于同步模拟系统的操作，并且第二时钟信号被配置为用于同步数字系统的操作。 该方法包括使用模拟系统的相位检测器来测量相对于第二时钟信号的第一时钟信号的定时; 并且该方法包括控制数字系统的延迟元件，以基于相位检测器的测量来调节定时，以抑制模拟系统中的噪声。

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