公开(公告)号：US11239210B2

公开(公告)日：2022-02-01

申请号：US17124762

申请日：2020-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan Woo ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US10916525B2

公开(公告)日：2021-02-09

申请号：US16125975

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan Woo ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US20190279963A1

公开(公告)日：2019-09-12

申请号：US16125975

申请日：2018-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan WOO ,  Je Min Ryu ,  Reum Oh ,  Moonhee Oh ,  BumSuk Lee

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.

公开(公告)号：US10671464B2

公开(公告)日：2020-06-02

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/0802 ,  G11C16/10 ,  G06F11/10 ,  G11C29/48 ,  G11C29/04

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.

公开(公告)号：US20180189127A1

公开(公告)日：2018-07-05

申请号：US15850604

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moonhee Oh ,  Je Min Ryu ,  Reum Oh ,  Jaeyoun Youn

IPC: G06F11/07 ,  G11C16/10 ,  G11C29/48 ,  G06F12/0802

CPC classification number: G06F11/0721 ,  G06F11/0736 ,  G06F11/1048 ,  G06F12/0802 ,  G11C16/10 ,  G11C29/48 ,  G11C2029/0409

Abstract: A memory device includes a command decoder and a status circuit. The command decoder decodes a command. The status circuit sequentially stores operation information of the memory device determined based on the decoded command and outputs at least one of the sequentially stored operation information in response to an output control signal.