公开(公告)号：US20230320080A1

公开(公告)日：2023-10-05

申请号：US18093561

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Woojin JEONG ,  Hui-Jung KIM

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor memory device includes an active portion defined by a device isolation pattern, the active portion including a first impurity region located at a center portion of the active portion and a second impurity region located at an end portion of the active portion, a word line provided on the active portion and extending in a first direction, a bit line provided on the word line and extending in a second direction crossing the first direction, a bit line contact provided between the bit line and the first impurity region of the active portion, a storage node pad provided on the second impurity region of the active portion, and a storage node contact provided on the storage node pad and at a side of the bit line.

公开(公告)号：US20240188285A1

公开(公告)日：2024-06-06

申请号：US18509539

申请日：2023-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjun KIM ,  Hyosub KIM ,  Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315

Abstract: The semiconductor device includes an active pattern; a gate structure in an upper portion of the active pattern; a bit line structure on the active pattern, the bit line structure including a first metal; a first spacer on a sidewall of the bit line structure, the first spacer including an oxide of a second metal that has an ionization energy smaller than that of the first metal; a second spacer on an outer sidewall of the first spacer, the second spacer including an oxide of a third metal; a third spacer on a lower portion of an outer sidewall of the second spacer, the third spacer including a nitride; a fourth spacer on an upper portion of the outer sidewall of the second spacer and the third spacer; a fifth spacer and a sixth spacer sequentially stacked in a horizontal direction from an outer sidewall of the fourth spacer.

公开(公告)号：US20230371235A1

公开(公告)日：2023-11-16

申请号：US18078217

申请日：2022-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Kiseok LEE

IPC: H10B12/00

CPC classification number: H01L27/10814

Abstract: A semiconductor device includes a substrate including an active region, a word line structure crossing the active region and extending in a first direction, a bit line structure extending in a second direction, a bit line contact electrically connecting a first impurity region of the active region to the bit line structure, a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, and a contact barrier layer covering at least a portion of the bit line contact, wherein the bit line contact includes a lower portion having a first width and an upper portion on the lower portion and having a second width, the first width is greater than the second width, and the contact barrier layer covers a bottom surface and a side surface of the lower portion.

公开(公告)号：US20230247822A1

公开(公告)日：2023-08-03

申请号：US18072885

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Junhyeok AHN ,  Hyosub KIM ,  Sohyun PARK

IPC: H10B12/00

CPC classification number: H01L27/10805

Abstract: A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

公开(公告)号：US20240155833A1

公开(公告)日：2024-05-09

申请号：US18341394

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Euna KIM ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate having an active region; word line structures in the substrate and extending in parallel to each other in a first horizontal direction; bit line structures on the substrate and the word line structures and extending in parallel to each other in a second horizontal direction that intersects the first horizontal direction; storage node contacts on a side wall of each of the bit line structures and electrically connected to the active region; and a fence structure having first line pattern portions on the word line structures and extending in the first horizontal direction, second line pattern portions extending in the second horizontal direction, and pillar portions extending from the first line pattern portions between the bit line structures in a vertical direction that is perpendicular to an upper surface of the substrate.

公开(公告)号：US20240130116A1

公开(公告)日：2024-04-18

申请号：US18376022

申请日：2023-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Sohyun PARK

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/485

Abstract: A semiconductor device includes a substrate having an active region; a bit line structure on the substrate and extending in one direction; a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and a storage node contact disposed on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, wherein the storage node contact includes a vertical extension portion extending in a vertical direction, perpendicular to an upper surface of the substrate, and a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, parallel to the upper surface of the substrate.

公开(公告)号：US20230320074A1

公开(公告)日：2023-10-05

申请号：US17948796

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jongmin KIM ,  Chansic YOON ,  Hyosub KIM ,  Sohyun PARK ,  Junhyeok AHN

IPC: H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10814 ,  H01L29/41725

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

公开(公告)号：US20230284430A1

公开(公告)日：2023-09-07

申请号：US18098202

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/485 ,  H10B12/315

Abstract: A semiconductor apparatus includes: a substrate in which a plurality of active areas are provided; a plurality of word lines formed on the substrate and located in a plurality of word line trenches extending in a first direction parallel to a top surface of the substrate; a plurality of bit line structures formed on the substrate, and extending in a second direction parallel to the top surface of the substrate and crossing the first direction; and a plurality of cell pad structures at least partially overlapping the plurality of active areas with the plurality of bit line structures therebetween, wherein each of the plurality of cell pad structures includes a pair of first side walls extending in the first direction and a pair of second side walls extending in a diagonal direction inclined with respect to the first direction and the second direction.

公开(公告)号：US20240381624A1

公开(公告)日：2024-11-14

申请号：US18489472

申请日：2023-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN

IPC: H10B12/00

Abstract: An embodiment provides a manufacturing method of a semiconductor device, including: forming first and second word lines in a substrate, wherein respective ends of the first and second word lines are connected to each other; forming a first separation groove between the first word line and the second word line, wherein the first separation groove includes a first insulating layer; and forming first and second bit lines on the substrate.

公开(公告)号：US20240357803A1

公开(公告)日：2024-10-24

申请号：US18541559

申请日：2023-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongmin CHOI ,  Hyo-sub KIM ,  Sangkyu SUN ,  Junhyeok AHN ,  Jay-bok CHOI

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction, an active pattern on the cell block region, a bit line provided on the active pattern and extended in the first direction, a first insulating structure in contact with the bit line, and a contact plug electrically connected to the bit line. The bit line may include a first curved portion, a first linear portion connected to the first curved portion, and a first intervening portion connected to the first curved portion. The contact plug may be overlapped with the first curved portion.