公开(公告)号：US20240155833A1

公开(公告)日：2024-05-09

申请号：US18341394

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Euna KIM ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate having an active region; word line structures in the substrate and extending in parallel to each other in a first horizontal direction; bit line structures on the substrate and the word line structures and extending in parallel to each other in a second horizontal direction that intersects the first horizontal direction; storage node contacts on a side wall of each of the bit line structures and electrically connected to the active region; and a fence structure having first line pattern portions on the word line structures and extending in the first horizontal direction, second line pattern portions extending in the second horizontal direction, and pillar portions extending from the first line pattern portions between the bit line structures in a vertical direction that is perpendicular to an upper surface of the substrate.

公开(公告)号：US20230262962A1

公开(公告)日：2023-08-17

申请号：US18107589

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso MYUNG ,  Keunnam KIM ,  Euna KIM ,  Huijung KIM ,  Sangho LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having an active area, bit line structures on the substrate, the bit line structures including an insulating spacer on each sidewall thereof, a buried contact between the bit line structures, the buried contact being connected to the active area, an insulation capping pattern on each of the bit line structures, a barrier conductive layer covering side surfaces of the insulation capping pattern, and an upper surface and side surfaces of the insulating spacer, and a landing pad electrically connected to the buried contact, the landing pad vertically overlapping one of the bit line structures on the insulation capping pattern and the barrier conductive layer.