公开(公告)号：US08836372B1

公开(公告)日：2014-09-16

申请号：US13782631

申请日：2013-03-01

Applicant: Raytheon Company

Inventor： Kenneth E. Prager ,  Lloyd J. Lewins ,  Harry Marr ,  Julia Karl ,  Michael Vahey

IPC: H03K19/00

CPC classification number: H03K19/0008

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract translation: 数字信号处理装置包括具有被配置为处理数字数据的一个或多个元件的数字电路装置; 电源，被配置为传递用于所述一个或多个元件的可控工作电压; 控制逻辑被配置为从所述一个或多个元件中的每一个接收反馈信号，所述反馈信号指示数据正在通过每个单独元件移动的速率; 以及所述控制逻辑被配置为将控制信号输出到所述电源，以便响应于在其中检测到的工作负荷减少而使所述电源降低所述一个或多个元件的工作电压，并且使所述电源增加所述操作 响应于其中检测到的增加的工作负载，一个或多个管道的电压。

公开(公告)号：US20140250313A1

公开(公告)日：2014-09-04

申请号：US13782546

申请日：2013-03-01

Applicant: RAYTHEON COMPANY

Inventor： Harry Marr ,  Kenneth E. Prager ,  Julia Karl ,  Lloyd J. Lewins

IPC: G06F1/32

CPC classification number: H03K19/096 ,  G06F7/57 ,  G06F9/3871

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract translation: 异步流水线结构包括多个功能块，其包括动态逻辑，每个块响应于施加到其上的预充电控制信号预充电到空闲状态，每个块在预充电时接收输入数据以进行处理，并保持生成的输出数据 从而在评估阶段期间，独立于输入数据的复位; 对于每个块，完成检测器电路耦合到功能块的输出，完成检测器电路产生指示块的输出处数据有效或不存在的确认信号; 并且对于每个块，产生预充电信号的预充电控制电路，其中对于给定的块，对预充电控制电路的第一输入包括来自下游完成检测器的确认信号，并且预充电控制电路的第二输入包括预充电信号 来自上游预充电控制电路。

公开(公告)号：US20140247088A1

公开(公告)日：2014-09-04

申请号：US13782631

申请日：2013-03-01

Applicant: RAYTHEON COMPANY

Inventor： Kenneth E. Prager ,  Lloyd J. Lewins ,  Harry Marr ,  Julia Karl ,  Michael Vahey

IPC: H03K19/00

CPC classification number: H03K19/0008

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract translation: 数字信号处理装置包括具有被配置为处理数字数据的一个或多个元件的数字电路装置; 电源，被配置为传递用于所述一个或多个元件的可控工作电压; 控制逻辑被配置为从所述一个或多个元件中的每一个接收反馈信号，所述反馈信号指示数据正在通过每个单独元件移动的速率; 以及所述控制逻辑被配置为将控制信号输出到所述电源，以便响应于在其中检测到的工作负荷减少而使所述电源降低所述一个或多个元件的工作电压，并且使所述电源增加所述操作 响应于其中检测到的增加的工作负载，一个或多个管道的电压。

公开(公告)号：US09438233B1

公开(公告)日：2016-09-06

申请号：US14839997

申请日：2015-08-30

Applicant: Raytheon Company

Inventor： Harry B. Marr ,  Kenneth E. Prager ,  Julia L. Karl ,  Daniel Thompson

IPC: H03K19/20 ,  H03K19/094 ,  H03K19/00 ,  H03K19/08

CPC classification number: H03K19/0013 ,  H03K19/0806

Abstract: A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.

Abstract translation: 低功率数字逻辑架构具有与标准数字逻辑相同的逻辑和电压电平特性。 逻辑开关和一对单向开关用于控制开关电感电容器（SLC）电路中的电荷流动方向，允许电感器从负载电容器的一侧向前拉动负载到另一侧 两者都切换电容器顶部的逻辑状态，并将电荷循环并存储在电容器本身中。

公开(公告)号：US09281820B2

公开(公告)日：2016-03-08

申请号：US13782546

申请日：2013-03-01

Applicant: Raytheon Company

Inventor： Harry Marr ,  Kenneth E. Prager ,  Julia Karl ,  Lloyd J. Lewins

IPC: G06F7/57 ,  H03K19/096

CPC classification number: H03K19/096 ,  G06F7/57 ,  G06F9/3871

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract translation: 异步流水线结构包括多个功能块，其包括动态逻辑，每个块响应于施加到其上的预充电控制信号预充电到空闲状态，每个块在预充电时接收输入数据以进行处理，并保持生成的输出数据 从而在评估阶段期间，独立于输入数据的复位; 对于每个块，完成检测器电路耦合到功能块的输出，完成检测器电路产生指示块的输出处数据有效或不存在的确认信号; 并且对于每个块，产生预充电信号的预充电控制电路，其中对于给定块，对于预充电控制电路的第一输入包括来自下游完成检测器的确认信号，并且到预充电控制电路的第二输入包括预充电信号 来自上游预充电控制电路。