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公开(公告)号：US11340686B2
公开(公告)日：2022-05-24
申请号：US16947973
申请日：2020-08-26
申请人： Rambus Inc.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , H03L7/081
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US10761587B2
公开(公告)日：2020-09-01
申请号：US16193247
申请日：2018-11-16
申请人： RAMBUS INC.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , H03L7/081
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20170052584A1
公开(公告)日：2017-02-23
申请号：US15248364
申请日：2016-08-26
申请人： RAMBUS INC.
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
摘要翻译： 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。
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公开(公告)号：US09431089B2
公开(公告)日：2016-08-30
申请号：US14405910
申请日：2013-06-10
申请人： RAMBUS INC.
IPC分类号： G11C8/00 , G11C11/4076 , G11C7/10 , G11C7/22 , G11C11/4093 , H03L7/081 , G11C7/04
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
摘要翻译： 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。
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公开(公告)号：US20170308144A1
公开(公告)日：2017-10-26
申请号：US15589651
申请日：2017-05-08
申请人： RAMBUS INC.
IPC分类号： G06F1/32 , G06F5/06 , G11C7/10 , G11C11/4076 , G11C7/22 , G11C11/4093 , H03L7/081 , G11C7/04
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20220350390A1
公开(公告)日：2022-11-03
申请号：US17748704
申请日：2022-05-19
申请人： Rambus Inc.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20210041932A1
公开(公告)日：2021-02-11
申请号：US16947973
申请日：2020-08-26
申请人： Rambus Inc.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20190171272A1
公开(公告)日：2019-06-06
申请号：US16193247
申请日：2018-11-16
申请人： RAMBUS INC.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4076 , G06F1/3234 , G06F5/06 , G06F1/3287 , G11C11/4093
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US09645631B2
公开(公告)日：2017-05-09
申请号：US15248364
申请日：2016-08-26
申请人： RAMBUS INC.
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20240345646A1
公开(公告)日：2024-10-17
申请号：US18643714
申请日：2024-04-23
申请人： Rambus Inc.
IPC分类号： G06F1/324 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093 , H03L7/081
CPC分类号： G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G06F2205/067 , G11C7/04 , G11C2207/2272 , H03L7/0816
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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