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公开(公告)号：US20200311859A1
公开(公告)日：2020-10-01
申请号：US16368782
申请日：2019-03-28
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Nigel POOLE , Zilin YING , Ling Feng HUANG , Donghyun KIM , Chun YU , Tzun-Wei LEE , Xuefeng TANG , Shambhoo KHANDELWAL , Hongjiang SHANG , Elina KAMENETSKAYA , Zhu LIANG , Cary ROBINS
Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, multiple processing units can be in a graphics processing pipeline of a GPU. The apparatus can also group the multiple processing units into one or more processing unit clusters. In some aspects, each of the one or more processing unit clusters can correspond to one or more context registers. Additionally, the apparatus can determine one or more context states of the one or more context registers in each of the one or more processing unit clusters. Also, the apparatus can implement one or more execution counters corresponding to at least one of the one or more processing unit clusters in the graphics processing pipeline, where each of the one or more execution counters includes an execution value.
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公开(公告)号：US20200020067A1
公开(公告)日：2020-01-16
申请号：US16035372
申请日：2018-07-13
Applicant: QUALCOMM Incorporated
Inventor： Jian LIANG , Tao WANG , Chun YU , Andrew Evan GRUBER , Donghyun KIM , Nigel POOLE , Tzun-Wei LEE , Shambhoo KHANDELWAL
Abstract: A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.
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