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公开(公告)号：US20240078735A1
公开(公告)日：2024-03-07
申请号：US18067837
申请日：2022-12-19
Applicant: QUALCOMM Incorporated
Inventor： Jian Liang , Andrew Evan Gruber , Tao Wang , Xuefeng Tang , Vishwanath Shashikant Nikam , Nigel Poole , Kalyan Kumar Bhiravabhatla , Fei Xu , Zilin Ying
IPC: G06T15/00
CPC classification number: G06T15/005
Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.
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Patent Agency Ranking
公开(公告)号：US20200013137A1
公开(公告)日：2020-01-09
申请号：US16028151
申请日：2018-07-05
Applicant: QUALCOMM Incorporated
Inventor： Richard Hammerstone , Nigel Poole , Thomas Edwin Frisinger , Andrew Evan Gruber , Anisha Datla
Abstract: Methods, systems, and devices for rendering are described. A device may divide a frame into a plurality of bins. The device may generate a command stream containing multiple repetitions of a fixed-stride draw table (FSDT), where each repetition of the FSDT includes a respective state vector for one or more hardware registers of a set of hardware registers. The device may identify, for each bin, a subset of the multiple repetitions of the FSDT in the command stream that include a live draw call. The device may execute, using the set of hardware registers, one or more rendering commands for each bin based at least in part on the corresponding subset of the multiple repetitions of the FSDT.
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公开(公告)号：US10748239B1
公开(公告)日：2020-08-18
申请号：US16290761
申请日：2019-03-01
Applicant: QUALCOMM Incorporated
Inventor： Nigel Poole , Xuefeng Tang , Jian Liang
Abstract: The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.
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公开(公告)号：US11372645B2
公开(公告)日：2022-06-28
申请号：US16900814
申请日：2020-06-12
Applicant: QUALCOMM Incorporated
Inventor： Nigel Poole , Joohi Mittal
Abstract: Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.
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公开(公告)号：US20240428364A1
公开(公告)日：2024-12-26
申请号：US18341233
申请日：2023-06-26
Applicant: QUALCOMM Incorporated
Inventor： Nigel Poole , Edwin Jose Africano
Abstract: Disclosed is a method for rendering a frame. The method is executed by a graphics processor and comprises dividing the frame into a plurality of bins. For each bin of the plurality of bins, the method comprises fetching a subset of entries corresponding to visible draw calls of a fixed stride draw table (FSDT). The FSDT comprises a plurality of entries corresponding to visible and invisible draw calls for the bin, wherein a visible draw call comprises instructions for drawing one or more pixels which are visible within the bin and wherein an invisible draw call only comprises instructions for drawing pixels which are invisible within the bin. The disclosed method further comprises executing the fetched subset of entries corresponding to visible draw calls.
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公开(公告)号：US12002142B2
公开(公告)日：2024-06-04
申请号：US17373718
申请日：2021-07-12
Applicant: QUALCOMM Incorporated
Inventor： Tushar Garg , Thomas Edwin Frisinger , Nigel Poole , Vishwanath Shashikant Nikam , Vijay Kumar Donthireddy
CPC classification number: G06T15/005 , G06F11/3485 , G06T1/20
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.
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