公开(公告)号：US20150106538A1

公开(公告)日：2015-04-16

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US09213487B2

公开(公告)日：2015-12-15

申请号：US14055761

申请日：2013-10-16

Applicant: QUALCOMM Incorporated

Inventor： Narasimhan Vasudevan ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0671 ,  G06F13/1668 ,  G11C7/10 ,  Y02D10/14

Abstract: A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.

Abstract translation: 本文描述了用于存储器读取的接收器架构。 在一个实施例中，存储器接口包括多个发射器，其中多个发射器中的每一个被配置成通过多个I / O通道中的相应一个发射数据到存储器装置。 所述存储器接口还包括多个接收器，其中所述多个接收器中的每一个接收器耦合到所述多个发射器中的相应一个，并且被配置为通过所述多个I / O中的相应一个I / O从所述存储器装置接收数据 频道 多个接收机被分组在一起，位于远离多个发射机的接收机子系统中。

公开(公告)号：US20150109034A1

公开(公告)日：2015-04-23

申请号：US14056861

申请日：2013-10-17

Applicant: QUALCOMM INCORPORATED

Inventor： Narasimhan Vasudevan ,  Zhiqin Chen ,  Li Pan ,  Michael Thomas Fertsch ,  Nan Chen

IPC: H03L7/08

CPC classification number: H03L7/0995 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0816

Abstract: A delay architecture for reducing downtime during frequency switching is described herein. In one embodiment, an adjustable delay circuit comprises a phase-locked loop (PLL) or a delay-locked loop (DLL) configured to generate a bias voltage, and a plurality of delay elements coupled in series, wherein each of the delay elements is biased by the bias voltage. The adjustable delay circuit also comprises a multiplexer coupled to outputs of two or more of the delay elements, wherein each of the outputs corresponds to a different delay of an input signal, and wherein the multiplexer is configured to select one of the outputs based on a data frequency of a memory interface.

Abstract translation: 这里描述了用于在频率切换期间减少停机时间的延迟架构。 在一个实施例中，可调延迟电路包括被配置为产生偏置电压的锁相环（PLL）或延迟锁定环（DLL）以及串联耦合的多个延迟元件，其中每个延迟元件是 由偏置电压偏置。 可调延迟电路还包括耦合到两个或更多个延迟元件的输出的多路复用器，其中每个输出对应于输入信号的不同延迟，并且其中多路复用器被配置为基于 存储器接口的数据频率。