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公开(公告)号:US20240419963A1
公开(公告)日:2024-12-19
申请号:US18333839
申请日:2023-06-13
Applicant: QUALCOMM Incorporated
Inventor: Mustafa KESKIN , Shruti CHITTAWADGI , Omprakash GUNIYA MOHAN RAM , Christopher KOOB , Andriy TEMKO , Venkatarakesh Kumar MAMIDI
Abstract: Certain aspects of the present disclosure provide techniques and apparatus for distributing a workload across computing devices within a distributed computing system. An example method generally includes receiving, from at least one respective computing device of a plurality of computing devices in a distributed computing environment, information defining a respective power neural network. The respective power neural network generally is trained to predict power utilization for the respective computing device for a task to be executed on the respective computing device. For one or more computing devices, power utilization is predicted for a workload to be executed within the distributed computing environment based on respective power neural networks associated with the one or more computing devices. Instructions to execute at least a portion of the workload based on the predicted power utilizations for the one or more computing devices are transmitted to the plurality of computing devices.
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公开(公告)号:US20220113901A1
公开(公告)日:2022-04-14
申请号:US17068293
申请日:2020-10-12
Applicant: QUALCOMM Incorporated
Inventor: Andrew Edmund TURNER , George PATSILARAS , Zhenbiao MA , Subbarao PALACHARLA , Bohuslav RYCHLIK , Tarek ZGHAL , Christopher KOOB
IPC: G06F3/06
Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.
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公开(公告)号:US20250156396A1
公开(公告)日:2025-05-15
申请号:US18509115
申请日:2023-11-14
Applicant: QUALCOMM Incorporated
Inventor: Richard SENIOR , Sundeep KUSHWAHA , Scott Russell BAUER , Gurvinder Singh CHHABRA , Norris GENG , Christopher KOOB , Sergei LARIN , Vipin SALI , Murali SOMANCHY , Aleksandr Sergeevich TARASIKOV
Abstract: Aspects of the disclosure are directed to data integrity detection. In accordance with one aspect, an apparatus including a compressed data sector configured to store a compressed data; a meta data sector coupled to the compressed data sector, the meta data sector configured to indicate an invalid meta data index; and a compression/decompression engine coupled to the meta data sector, the compression/decompression engine configured to compress an original data to generate the compressed data and further configured to decompress the compressed data to generate a decompressed data.
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公开(公告)号:US20250165143A1
公开(公告)日:2025-05-22
申请号:US18513393
申请日:2023-11-17
Applicant: QUALCOMM Incorporated
Inventor: Kan WANG , Norris GENG , Richard SENIOR , Christopher KOOB , Pranav VERMA , Suresh Kumar VENKUMAHANTI , Gurvinder Singh CHHABRA
IPC: G06F3/06
Abstract: A method for reducing a memory footprint of data stored in a compressed memory subsystem is described. The method includes selecting a read/write data to store in the compressed memory subsystem. The method also includes searching a first compressed data storage pool of the compressed memory subsystem corresponding to a compressed size of the read/write data to identify a first free data block. The method further includes storing the read/write data in a second free data block from a second compressed data storage pool of the compressed memory subsystem corresponding to a compressed size of the read/write data if the first compressed data storage pool is exhausted.
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公开(公告)号:US20190138311A1
公开(公告)日:2019-05-09
申请号:US15805935
申请日:2017-11-07
Applicant: QUALCOMM Incorporated
Inventor: Peter SASSONE , Christopher KOOB , Suresh Kumar VENKUMAHANTI
CPC classification number: G06F9/30196 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
Abstract: Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.
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