公开(公告)号：US20160037453A1

公开(公告)日：2016-02-04

申请号：US14814321

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Thiagarajan SIVANADYAN ,  Prasad KADIRI ,  Neelakanta Venkata Seshachalam CHIMMAPUDI ,  Ammar KITABI ,  Kamalakar GANTI ,  Chintan SHAH ,  Aziz GHOLMIEH

IPC: H04W52/02 ,  H04L5/00 ,  H04L1/18

CPC classification number: H04W52/0235 ,  H04L1/1812 ,  H04L5/0055 ,  H04W52/146 ,  H04W52/44 ,  H04W52/48 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus configured to establish a wireless connection to a first network, tune away from the first network for a first predetermined interval, tune back to the first network after the first predetermined interval, enter a power control freeze state for a second predetermined interval after tuning back to the first network, send a plurality of transmissions to the first network during the second predetermined interval, determine if a number of the plurality of transmissions that are not received by the first network exceeds a first threshold or if a number of the plurality of transmissions that are retransmitted to the first network exceeds a second threshold, and exit the power control freeze state when it is determined that the first threshold is exceeded or when it is determined that the second threshold is exceeded.

Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 所述装置被配置为建立到第一网络的无线连接，从第一网络调出第一预定间隔，在第一预定间隔之后回到第一网络，在调谐之后进入第二预定间隔的功率控制冻结状态 回到所述第一网络，在所述第二预定间隔期间向所述第一网络发送多个传输，确定所述第一网络未接收的所述多个传输的数量是否超过第一阈值，或者如果所述多个 重传到第一网络的传输超过第二阈值，并且当确定超过第一阈值或何时确定超过第二阈值时，退出功率控制冻结状态。

公开(公告)号：US20160293234A1

公开(公告)日：2016-10-06

申请号：US14742706

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Stephen Edward LILES ,  Satendra Kumar MAURYA ,  Kunal GARG ,  Chiaming CHAI ,  Chintan SHAH

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract translation: 异步存储器包括存储器阵列，读出放大器，输出锁存器和控制器。 响应于来自外部电路的请求读取操作的时钟信号，控制器将时钟信号提供给存储器阵列以读取数据，并且控制读出放大器和输出锁存器以提供触发器主器件和从器件的功能 使得通过输出锁存器到外部电路的读操作延迟从两个顺序读周期的第一读周期中去除。