公开(公告)号：US20140223250A1

公开(公告)日：2014-08-07

申请号：US14172292

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Wei Chen ,  Yucong Tao ,  Matthew L. Severson ,  Jeffrey R. Gemar ,  Chang Yong Yang

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3008 ,  G01R31/318575

Abstract: Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.

Abstract translation: 提供了用于测试集成电路的装置和方法。 在用于测试集成电路的示例性方法中，将测试控制器和功率管理器集成到集成电路的主电源域中。 测试控制器可以与联合测试动作组兼容。 使用电源管理器生成隔离信号。 隔离信号可以包括被配置为隔离集成电路的输入 - 输出端口的冻结信号和被配置为隔离集成电路的功能模块的钳位信号中的至少一个。 隔离信号可以存储在由测试控制器控制的边界扫描寄存器中。 主电源区域与具有隔离信号的集成电路的电源可折叠域隔离。 电源可折叠域的功能崩溃。 当电源崩溃时，使用测试控制器和电源管理器测试电源可折叠域。 功率可折叠域的测试可以包括测试电源电流。 当功率可折叠域的电源被折叠时，电平移位器输出可以基于来自功率可折叠域的预折叠输入而保持恒定到输出电平。

公开(公告)号：US20140281643A1

公开(公告)日：2014-09-18

申请号：US13801375

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Kris TIRI ,  Matthew Scott McGregor ,  Yucong Tao

IPC: G06F21/50

CPC classification number: G06F21/57 ,  G06F1/04 ,  G06F1/06 ,  G06F11/0721 ,  G06F11/076 ,  G06F21/00 ,  G06F21/55 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/725

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

Abstract translation: 公开了一种检测时钟篡改的方法。 在该方法中，提供多个可复位延迟线段。 在与最小延迟时间相关联的可复位延迟线段与与最大延迟时间相关联的可复位延迟线段之间的可复位延迟线段分别与离散增加的延迟时间相关联。 在与时钟相关联的时钟评估时间段期间提供单调信号。 使用多个可复位延迟线段中的每一个来延迟单调信号以产生相应的多个延迟单调信号。 时钟用于触发使用多个延迟单调信号来检测时钟故障的评估电路。

公开(公告)号：US09607153B2

公开(公告)日：2017-03-28

申请号：US13801375

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Kris Tiri ,  Matthew Scott McGregor ,  Yucong Tao

IPC: G06F11/30 ,  G06F1/00 ,  H04L29/06 ,  G06F11/00 ,  G06F21/57 ,  G06F1/06 ,  G06F1/04 ,  G06F11/07 ,  G06F21/72 ,  G06F21/55 ,  G06F21/00 ,  G06F21/70 ,  G06F21/60 ,  G06F21/71

CPC classification number: G06F21/57 ,  G06F1/04 ,  G06F1/06 ,  G06F11/0721 ,  G06F11/076 ,  G06F21/00 ,  G06F21/55 ,  G06F21/602 ,  G06F21/70 ,  G06F21/71 ,  G06F21/725

Abstract: Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

公开(公告)号：US09267989B2

公开(公告)日：2016-02-23

申请号：US14172292

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Wei Chen ,  Yucong Tao ,  Matthew L. Severson ,  Jeffrey R. Gemar ,  Chang Yong Yang

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/30 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/3008 ,  G01R31/318575

Abstract: Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.

Abstract translation: 提供了用于测试集成电路的装置和方法。 在用于测试集成电路的示例性方法中，将测试控制器和功率管理器集成到集成电路的主电源域中。 测试控制器可以与联合测试动作组兼容。 使用电源管理器生成隔离信号。 隔离信号可以包括被配置为隔离集成电路的输入 - 输出端口的冻结信号和被配置为隔离集成电路的功能模块的钳位信号中的至少一个。 隔离信号可以存储在由测试控制器控制的边界扫描寄存器中。 主电源区域与具有隔离信号的集成电路的电源可折叠域隔离。 电源可折叠域的功能崩溃。 当电源崩溃时，使用测试控制器和电源管理器测试电源可折叠域。 功率可折叠域的测试可以包括测试电源电流。 当功率可折叠域的电源被折叠时，电平移位器输出可以基于来自功率可折叠域的预折叠输入而保持恒定到输出电平。

公开(公告)号：US08908464B2

公开(公告)日：2014-12-09

申请号：US13765559

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： Gregory Ameriada Uvieghara ,  Michael Batenburg ,  Esin Terzioglu ,  Yucong Tao

IPC: G11C5/14 ,  G01R31/36

CPC classification number: G11C5/143 ,  G01R31/31719 ,  G01R31/3658 ,  G11C7/24

Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关联的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。

公开(公告)号：US20140226426A1

公开(公告)日：2014-08-14

申请号：US13765559

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Gregory Ameriada Uvieghara ,  Michael Batenburg ,  Esin Terzioglu ,  Yucong Tao

IPC: G11C5/14

CPC classification number: G11C5/143 ,  G01R31/31719 ,  G01R31/3658 ,  G11C7/24

Abstract: Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (NVM), test cells associated with the NVM are read first. The test cells share a common power supply with the NVM and output read values from the test cells are configured to deviate from values pre-programmed in the test cells when a subnormal read voltage is applied on the common power supply. Thus, by comparing the output read values with the pre-programmed values, it can be determined whether voltage of the common power supply is subnormal, wherein configuration information will be read incorrectly at a subnormal read voltage. If the voltage is subnormal, power up is aborted. Otherwise, power up is allowed to proceed by reading the configuration information from the NVM.

Abstract translation: 用于检测与集成电路上的次正常读取电压相关的电源攻击的系统和方法。 在启动集成电路的电源并且在从非易失性存储器（NVM）读取配置信息之前，首先读取与NVM相关的测试单元。 测试单元与NVM共用公共电源，并且当在公共电源上施加次正常读取电压时，来自测试单元的输出读取值被配置为偏离测试单元中预编程的值。 因此，通过将输出读取值与预编程值进行比较，可以确定公共电源的电压是否是次正常，其中配置信息将在非正常读取电压下读取不正确。 如果电压低于正常值，则上电将中止。 否则，可以通过从NVM读取配置信息来上电。