公开(公告)号：US10386904B2

公开(公告)日：2019-08-20

申请号：US15086054

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Christophe Denis Bernard Avoinne ,  Manokanthan Somasundaram ,  Sina Dena ,  Paul Christopher John Wiercienski ,  Bohuslav Rychlik ,  Steven John Halter ,  Jaya Prakash Subramaniam Ganasan ,  Myil Ramkumar ,  Dipti Ranjan Pal

IPC: G06F1/26 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F12/08

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US08910307B2

公开(公告)日：2014-12-09

申请号：US13715351

申请日：2012-12-14

Applicant: QUALCOMM Incorporated

Inventor： Sudeep Ravi Kottilingal ,  Gary Arthur Ciambella ,  Steven John Halter

IPC: G06F9/06 ,  H04N21/4385 ,  H04N21/426 ,  H04N21/443 ,  H04N21/835 ,  H04N21/4405 ,  G06F21/62 ,  H04N21/44 ,  H04L29/06

CPC classification number: G06F21/62 ,  G06F21/00 ,  H04L63/02 ,  H04N21/42623 ,  H04N21/42653 ,  H04N21/42692 ,  H04N21/43853 ,  H04N21/44004 ,  H04N21/4405 ,  H04N21/4431 ,  H04N21/4435 ,  H04N21/835

Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.

Abstract translation: 通常，本公开的方面涉及复制保护技术。 存储器中的区域可以被保护以在存储器中建立安全的存储器区域，该区域不被未经授权的客户端访问。 可以接收对存储在安全存储器区域中的视频内容进行解码的请求。 如果要解码的视频内容被存储在安全存储器区域中，则与硬件解码器相关联的第一MMU可以强制将视频内容解码为安全存储器区域中的一个或多个输出缓冲器的规则。 可以接收显示存储在安全存储器区域中的解码的视频内容的请求。 如果解码的视频内容存储在安全存储器区域中，则与硬件显示处理器相关联的第二MMU可以强制在硬件显示处理器和输出设备之间建立安全链路的规则。

公开(公告)号：US20130305342A1

公开(公告)日：2013-11-14

申请号：US13715351

申请日：2012-12-14

Applicant: QUALCOMM INCORPORATED

Inventor： Sudeep Ravi Kottilingal ,  Gary Arthur Ciambella ,  Steven John Halter

IPC: G06F21/62

CPC classification number: G06F21/62 ,  G06F21/00 ,  H04L63/02 ,  H04N21/42623 ,  H04N21/42653 ,  H04N21/42692 ,  H04N21/43853 ,  H04N21/44004 ,  H04N21/4405 ,  H04N21/4431 ,  H04N21/4435 ,  H04N21/835

Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.

Abstract translation: 通常，本公开的方面涉及复制保护技术。 存储器中的区域可以被保护以在存储器中建立安全的存储器区域，该区域不被未经授权的客户端访问。 可以接收对存储在安全存储器区域中的视频内容进行解码的请求。 如果要解码的视频内容被存储在安全存储器区域中，则与硬件解码器相关联的第一MMU可以强制将视频内容解码为安全存储器区域中的一个或多个输出缓冲器的规则。 可以接收显示存储在安全存储器区域中的解码的视频内容的请求。 如果解码的视频内容存储在安全存储器区域中，则与硬件显示处理器相关联的第二MMU可以强制在硬件显示处理器和输出设备之间建立安全链路的规则。