公开(公告)号：US20250103335A1

公开(公告)日：2025-03-27

申请号：US18475320

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Darshan Kumar Nandanwar ,  Sagar Bamashetti

IPC: G06F9/30

Abstract: A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.

公开(公告)号：US12282447B2

公开(公告)日：2025-04-22

申请号：US18473119

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Sharath Kumar Nagilla ,  Darshan Kumar Nandanwar

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/80

Abstract: A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

公开(公告)号：US12299301B2

公开(公告)日：2025-05-13

申请号：US18307686

申请日：2023-04-26

Applicant: QUALCOMM INCORPORATED

Inventor： Hithesh Hassan Lepaksha ,  Darshan Kumar Nandanwar ,  Sharath Kumar Nagilla

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0888 ,  G06F12/0897

Abstract: Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.

公开(公告)号：US11940914B2

公开(公告)日：2024-03-26

申请号：US17827302

申请日：2022-05-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Sharath Kumar Nagilla ,  Darshan Kumar Nandanwar ,  Nirav Narendra Desai ,  Venkata Biswanath Devarasetty

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/468

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

公开(公告)号：US11836086B1

公开(公告)日：2023-12-05

申请号：US17806291

申请日：2022-06-10

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Sharath Kumar Nagilla ,  Darshan Kumar Nandanwar ,  Nirav Narendra Desai ,  Venkata Biswanath Devarasetty

IPC: G06F12/0891 ,  G06F12/123 ,  G06F12/0895

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/124

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.