公开(公告)号：US20250103335A1

公开(公告)日：2025-03-27

申请号：US18475320

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan Lepaksha ,  Darshan Kumar Nandanwar ,  Sagar Bamashetti

IPC: G06F9/30

Abstract: A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.