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    DISTRIBUTED RAMP LINEARITY COMPENSATION CIRCUIT
    1.
    发明申请
    DISTRIBUTED RAMP LINEARITY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20250048002A1

    公开(公告)日：2025-02-06

    申请号：US18363469

    申请日：2023-08-01

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Nobuhiro Yanagisawa ,  Satoshi Sakurai ,  Tomoyasu Tate ,  Naoki Kitazawa ,  Kohei Harada

    IPC: H04N25/78 ,  H04N25/709 ,  H04N25/76

    Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS
    2.
    发明申请
    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS 有权

    公开(公告)号：US20250047995A1

    公开(公告)日：2025-02-06

    申请号：US18363473

    申请日：2023-08-01

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liang Zuo ,  Hiroaki Ebihara ,  Jing Jun Yi ,  Rui Wang ,  Satoshi Sakurai

    IPC: H04N25/677 ,  H04N25/766 ,  H04N25/772

    Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

    DYNAMIC CURRENT CONTROL FOR COLUMN ADC
    3.
    发明公开
    DYNAMIC CURRENT CONTROL FOR COLUMN ADC 审中-公开

    公开(公告)号：US20240291499A1

    公开(公告)日：2024-08-29

    申请号：US18176373

    申请日：2023-02-28

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu ,  Satoshi Sakurai ,  Kenny Geng

    IPC: H03M1/46

    CPC classification number: H03M1/466 ,  H03M1/462

    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

    Adaptive correlated multiple sampling
    5.
    发明授权
    Adaptive correlated multiple sampling 有权

    公开(公告)号：US12294804B2

    公开(公告)日：2025-05-06

    申请号：US18322431

    申请日：2023-05-23

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Jiayu Guo ,  Hiroaki Ebihara ,  Liang Zuo ,  Lihang Fan ,  Satoshi Sakurai

    IPC: H04N25/78 ,  H04N25/616

    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

    Gray code counting signal distribution system
    8.
    发明授权
    Gray code counting signal distribution system 有权

    公开(公告)号：US10659056B1

    公开(公告)日：2020-05-19

    申请号：US16440279

    申请日：2019-06-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Satoshi Sakurai ,  Hiroaki Ebihara

    IPC: H03K23/00 ,  H03M1/56 ,  H03M7/16

    Abstract: A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.

    Dynamic current control for column ADC
    10.
    发明授权
    Dynamic current control for column ADC 有权

    公开(公告)号：US12199632B2

    公开(公告)日：2025-01-14

    申请号：US18176373

    申请日：2023-02-28

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu ,  Satoshi Sakurai ,  Kenny Geng

    IPC: H03M1/46

    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

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