公开(公告)号：US11943545B2

公开(公告)日：2024-03-26

申请号：US17164961

申请日：2021-02-02

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Yoshinobu Tanaka ,  Atsushi Ishihara ,  Akira Ueno

IPC分类号： H04N23/80 ,  G11C11/413

CPC分类号： H04N23/80 ,  G11C11/413

摘要： An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

公开(公告)号：US20210160425A1

公开(公告)日：2021-05-27

申请号：US17164961

申请日：2021-02-02

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Yoshinobu Tanaka ,  Atsushi Ishihara ,  Akira Ueno

IPC分类号： H04N5/232 ,  G11C11/413

摘要： An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

公开(公告)号：US11842071B2

公开(公告)日：2023-12-12

申请号：US17735769

申请日：2022-05-03

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Ryusuke Tsuchida

IPC分类号： G06F3/06

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0673

摘要： A data transfer device includes: a plurality of masters each having a buffer and configured to calculate a remaining-time counter based on an amount of data in the buffer; a memory system configured to perform data transfer with the plurality of masters and having a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter configured to arbitrate the plurality of masters based on the remaining-time counter; and a remaining-time counter-adjusting part configured to add a remaining-time counter offset, which adjusts the remaining-time counter until the start of the memory access prohibition period, to at least one of the plurality of masters.

公开(公告)号：US11309898B2

公开(公告)日：2022-04-19

申请号：US17167374

申请日：2021-02-04

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Akira Ueno

IPC分类号： H03L7/099

摘要： A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

公开(公告)号：US20210159903A1

公开(公告)日：2021-05-27

申请号：US17167374

申请日：2021-02-04

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Akira Ueno

IPC分类号： H03L7/099

摘要： A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

公开(公告)号：US20220261179A1

公开(公告)日：2022-08-18

申请号：US17735769

申请日：2022-05-03

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Ryusuke Tsuchida

IPC分类号： G06F3/06

摘要： A data transfer device includes: a plurality of masters each having a buffer and configured to calculate a remaining-time counter based on an amount of data in the buffer; a memory system configured to perform data transfer with the plurality of masters and having a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter configured to arbitrate the plurality of masters based on the remaining-time counter; and a remaining-time counter-adjusting part configured to add a remaining-time counter offset, which adjusts the remaining-time counter until the start of the memory access prohibition period, to at least one of the plurality of masters.

公开(公告)号：US11153478B2

公开(公告)日：2021-10-19

申请号：US17136311

申请日：2020-12-29

申请人： OLYMPUS CORPORATION

发明人： Yoshinobu Tanaka ,  Atsushi Ishihara ,  Yutaka Murata ,  Akira Ueno

IPC分类号： H04N5/232

摘要： An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

公开(公告)号：US20210120173A1

公开(公告)日：2021-04-22

申请号：US17136311

申请日：2020-12-29

申请人： OLYMPUS CORPORATION

发明人： Yoshinobu Tanaka ,  Atsushi Ishihara ,  Yutaka Murata ,  Akira Ueno

IPC分类号： H04N5/232

摘要： An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.