公开(公告)号：US09479184B2

公开(公告)日：2016-10-25

申请号：US12858315

申请日：2010-08-17

申请人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

发明人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

IPC分类号： H03L7/087 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03L7/087 ,  H03L2207/06

摘要： A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

摘要翻译： 应用于锁相环（PLL）的频率校准装置包括频率检测模块和搜索模块。 频率检测模块包括第一计数器，第二计数器和比较单元。 在监视期间，第一计数器和第二计数器分别产生第一计数和第二计数。 比较单元将第一计数与第二计数进行比较，以生成指示至少三种情况的比较结果。 搜索模块根据比较结果选择频率曲线，并根据频率曲线校准压控振荡器（VCO）的配置。

公开(公告)号：US08731025B2

公开(公告)日：2014-05-20

申请号：US12911071

申请日：2010-10-25

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H04B1/00 ,  H04J3/24 ,  H04B1/40

CPC分类号： H03C3/0966

摘要： An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

摘要翻译： 偏移锁相环（PLL）发射机包括产生第一时钟信号的时钟发生器; 检测器，其检测输入数据信号和反馈数据信号之间的相位差，以产生控制信号; 耦合到所述检测器的受控振荡器，其根据所述控制信号产生输出数据信号; 耦合到受控振荡器和时钟发生器的混频器，其根据第一时钟信号混合输出数据信号以产生反馈数据信号; 以及耦合到所述检测器和所述受控振荡器的控制电路，其通过第一步距离和小于所述第一步距离的第二步距离之一调节所述受控振荡器的工作频率曲线，使得所述控制信号基本相等 达到预定值。

公开(公告)号：US20110080196A1

公开(公告)日：2011-04-07

申请号：US12886112

申请日：2010-09-20

申请人： Yao-Chi Wang ,  Ming-Yu Hsieh ,  Shih-Chieh Yen

发明人： Yao-Chi Wang ,  Ming-Yu Hsieh ,  Shih-Chieh Yen

IPC分类号： H03L7/08

CPC分类号： H03L7/103 ,  H03L2207/14

摘要： A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

摘要翻译： 用于控制VCO在接收到频率锁定信号之后处理相位锁定过程的压控振荡器（VCO）控制电路包括操作频率控制器和判断单元。 耦合到VCO和判断单元的工作频率控制器产生VCO的第一控制码和第二控制码之一。 耦合到VCO的输入端的判断单元根据输入到VCO的电压控制信号产生锁相信号。 当工作频率控制器接收到频率锁定信号时，工作频率控制器产生第一控制码以控制VCO从第一候选VCO曲线切换到第二候选VCO曲线。 当工作频率控制器接收到相位锁定信号时，工作频率控制器产生第二控制码，以控制VCO从第二候选VCO曲线切换到第一候选VCO曲线。

公开(公告)号：US07948286B2

公开(公告)日：2011-05-24

申请号：US12862346

申请日：2010-08-24

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H03L7/06

CPC分类号： H03L7/1075 ,  H03L7/093 ,  H03L7/1072

摘要： A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module.

摘要翻译： 应用于锁相环（PLL）的环路带宽控制装置包括第一环路滤波器模块，第二环路滤波器模块，控制模块，第一交换模块和第二交换模块。 第一滤波器模块和第二环路滤波器模块分别输出第一电压和第二电压。 第二环路滤波器模块具有与第一环路滤波器模块不同的带宽。 根据第一电压和第二电压之一，控制模块产生带宽控制信号。 根据带宽控制信号，第一开关模块形成电荷泵与第一环路滤波器模块和第二环路滤波器模块之一的路径，第二开关模块在压控振荡器（VCO） 以及第一环路滤波器模块和第二环路滤波器模块之一。

公开(公告)号：US20110057696A1

公开(公告)日：2011-03-10

申请号：US12858315

申请日：2010-08-17

申请人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

发明人： Ming-Yu Hsieh ,  Shih-Chieh Yen ,  Yao-Chi Wang

IPC分类号： H03L7/06

CPC分类号： H03L7/099 ,  H03L7/087 ,  H03L2207/06

摘要： A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

摘要翻译： 应用于锁相环（PLL）的频率校准装置包括频率检测模块和搜索模块。 频率检测模块包括第一计数器，第二计数器和比较单元。 在监视期间，第一计数器和第二计数器分别产生第一计数和第二计数。 比较单元将第一计数与第二计数进行比较，以生成指示至少三种情况的比较结果。 搜索模块根据比较结果选择频率曲线，并根据频率曲线校准压控振荡器（VCO）的配置。

公开(公告)号：US20110122965A1

公开(公告)日：2011-05-26

申请号：US12911071

申请日：2010-10-25

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H04L27/00

CPC分类号： H03C3/0966

摘要： An offset phase-locked loop (PLL) transmitter comprises a clock generator that generates a first clock signal; a detector that detects a phase difference between an input data signal and a feedback data signal to generate a control signal; a controlled oscillator, coupled to the detector, that generates an output data signal according to the control signal; a mixer, coupled to the controlled oscillator and the clock generator, that mixes the output data signal according to the first clock signal to generate the feedback data signal; and a control circuit, coupled to the detector and the controlled oscillator, that adjusts the operating frequency curve of the controlled oscillator by one of a first step distance and a second step distance smaller than the first step distance such that the control signal is substantially equal to a predetermined value.

摘要翻译： 偏移锁相环（PLL）发射机包括产生第一时钟信号的时钟发生器; 检测器，其检测输入数据信号和反馈数据信号之间的相位差，以产生控制信号; 耦合到所述检测器的受控振荡器，其根据所述控制信号产生输出数据信号; 耦合到受控振荡器和时钟发生器的混频器，其根据第一时钟信号混合输出数据信号以产生反馈数据信号; 以及耦合到所述检测器和所述受控振荡器的控制电路，其通过第一步距离和小于所述第一步距离的第二步距离之一调节所述受控振荡器的工作频率曲线，使得所述控制信号基本相等 达到预定值。

公开(公告)号：US20110080199A1

公开(公告)日：2011-04-07

申请号：US12862346

申请日：2010-08-24

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Ming-Yu Hsieh

IPC分类号： H03L7/08

CPC分类号： H03L7/1075 ,  H03L7/093 ,  H03L7/1072

摘要： A loop bandwidth control apparatus applied to a phase locked loop (PLL) includes a first loop filter module, a second loop filter module, a control module, a first switching module, and a second switching module. The first filter module and the second loop filter module output a first voltage and a second voltage, respectively. The second loop filter module has a bandwidth different from that of the first loop filter module. According to one of the first voltage and the second voltage, the control module generates a bandwidth control signal. According to the bandwidth control signal, the first switching module forms a path between a charge pump and one of the first loop filter module and the second loop filter module, and the second switching module forms a path between a voltage-controlled oscillator (VCO) and one of the first loop filter module and the second loop filter module.

摘要翻译： 应用于锁相环（PLL）的环路带宽控制装置包括第一环路滤波器模块，第二环路滤波器模块，控制模块，第一交换模块和第二交换模块。 第一滤波器模块和第二环路滤波器模块分别输出第一电压和第二电压。 第二环路滤波器模块具有与第一环路滤波器模块不同的带宽。 根据第一电压和第二电压之一，控制模块产生带宽控制信号。 根据带宽控制信号，第一开关模块形成电荷泵与第一环路滤波器模块和第二环路滤波器模块之一的路径，第二开关模块在压控振荡器（VCO） 以及第一环路滤波器模块和第二环路滤波器模块之一。

公开(公告)号：US08629728B2

公开(公告)日：2014-01-14

申请号：US12886112

申请日：2010-09-20

申请人： Yao-Chi Wang ,  Ming-Yu Hsieh ,  Shih-Chieh Yen

发明人： Yao-Chi Wang ,  Ming-Yu Hsieh ,  Shih-Chieh Yen

IPC分类号： H03L7/00

CPC分类号： H03L7/103 ,  H03L2207/14

摘要： A voltage-controlled oscillator (VCO) control circuit, used for controlling a VCO to process phase locking procedure after receiving a frequency locking signal, comprises an operating frequency controller and a judgment unit. The operating frequency controller, coupled to the VCO and the judgment unit, generates one of a first control code and a second control code to the VCO. The judgment unit, coupled to an input end of the VCO, generates a phase locking signal according to a voltage control signal inputted to the VCO. When the operating frequency controller receives the frequency locking signal, the operating frequency controller generates a first control code to control the VCO to switch from a first candidate VCO curve to a second candidate VCO curve. When the operating frequency controller receives the phase locking signal, the operating frequency controller generates a second control code to control the VCO to switch from the second candidate VCO curve to the first candidate VCO curve.

摘要翻译： 用于控制VCO在接收到频率锁定信号之后处理相位锁定过程的压控振荡器（VCO）控制电路包括操作频率控制器和判断单元。 耦合到VCO和判断单元的工作频率控制器产生VCO的第一控制码和第二控制码之一。 耦合到VCO的输入端的判断单元根据输入到VCO的电压控制信号产生锁相信号。 当工作频率控制器接收到频率锁定信号时，工作频率控制器产生第一控制码以控制VCO从第一候选VCO曲线切换到第二候选VCO曲线。 当工作频率控制器接收到相位锁定信号时，工作频率控制器产生第二控制码，以控制VCO从第二候选VCO曲线切换到第一候选VCO曲线。

公开(公告)号：US08258878B2

公开(公告)日：2012-09-04

申请号：US12893662

申请日：2010-09-29

申请人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Hsu-Hung Chang

发明人： Shih-Chieh Yen ,  Yao-Chi Wang ,  Hsu-Hung Chang

IPC分类号： H03L7/00

CPC分类号： H03L7/183 ,  H03C3/0916 ,  H03C3/0975 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898

摘要： A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

摘要翻译： 锁相环（PLL）包括时钟产生电路，第一相位检测电路，第一环路滤波器，第一VCO，第一混频器和控制电路。 时钟发生电路产生第一时钟信号。 第一相位检测电路检测输入数据信号和反馈信号之间的相位差，并根据相位差生成检测输出信号。 耦合到第一相位检测电路的第一环路滤波器根据检测输出信号产生第一VCO控制信号。 耦合到第一VCO和时钟发生电路的第一混频器混合输出数据信号和第一时钟信号以产生反馈数据信号。 耦合到时钟发生电路和第一环路滤波器的控制电路，用于根据第一VCO控制信号调整第一时钟信号，以计算第一VCO的增益。

公开(公告)号：US20110102090A1

公开(公告)日：2011-05-05

申请号：US12893662

申请日：2010-09-29

申请人： SHIH-CHIEH YEN ,  Yao-Chi Wang ,  Hsu-Hung Chang

发明人： SHIH-CHIEH YEN ,  Yao-Chi Wang ,  Hsu-Hung Chang

IPC分类号： H03L7/00 ,  H03L7/06

CPC分类号： H03L7/183 ,  H03C3/0916 ,  H03C3/0975 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898

摘要： A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

摘要翻译： 锁相环（PLL）包括时钟产生电路，第一相位检测电路，第一环路滤波器，第一VCO，第一混频器和控制电路。 时钟发生电路产生第一时钟信号。 第一相位检测电路检测输入数据信号和反馈信号之间的相位差，并根据相位差生成检测输出信号。 耦合到第一相位检测电路的第一环路滤波器根据检测输出信号产生第一VCO控制信号。 耦合到第一VCO和时钟发生电路的第一混频器混合输出数据信号和第一时钟信号以产生反馈数据信号。 耦合到时钟发生电路和第一环路滤波器的控制电路，用于根据第一VCO控制信号调整第一时钟信号，以计算第一VCO的增益。