SEMICONDUCTOR PACKAGE STRUCTURE
    1.
    发明申请

    公开(公告)号:US20220367430A1

    公开(公告)日:2022-11-17

    申请号:US17739295

    申请日:2022-05-09

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor die, and a first capacitor. The substrate has a wiring structure. The redistribution layer is disposed over the substrate. The first semiconductor die is disposed over the redistribution layer. The first capacitor is disposed in the substrate and is electrically coupled to the first semiconductor die. The first capacitor includes a first capacitor substrate, a plurality of first capacitor cells, and a first through via. The first capacitor substrate has a first top surface and a first bottom surface. The first capacitor cells are disposed in the first capacitor substrate. The first through via is disposed in the first capacitor substrate and electrically couples the first capacitor cells to the wiring structure on the first top surface and the first bottom surface.

    SEMICONDUCTOR PACKAGE STRUCTURE
    4.
    发明公开

    公开(公告)号:US20230317580A1

    公开(公告)日:2023-10-05

    申请号:US18329721

    申请日:2023-06-06

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

    SEMICONDUCTOR PACKAGE STRUCTURE
    5.
    发明申请

    公开(公告)号:US20220223491A1

    公开(公告)日:2022-07-14

    申请号:US17545015

    申请日:2021-12-08

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

    SEMICONDUCTOR PACKAGE STRUCTURE
    6.
    发明申请

    公开(公告)号:US20220223512A1

    公开(公告)日:2022-07-14

    申请号:US17546191

    申请日:2021-12-09

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.

    SEMICONDUCTOR PACKAGE STRUCTURE
    7.
    发明申请

    公开(公告)号:US20220013441A1

    公开(公告)日:2022-01-13

    申请号:US17363459

    申请日:2021-06-30

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.

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