Image sensor with embedded light-measuring pixels and method of automatic exposure control using the same

    公开(公告)号:US10957729B2

    公开(公告)日:2021-03-23

    申请号:US16383920

    申请日:2019-04-15

    Applicant: MEDIATEK INC.

    Abstract: An apparatus is provided. The apparatus includes: a processor configured to perform operations including the steps of: receiving, from a sensor array of an image sensor, data sensed by the sensor array, the sensed data comprising image data and ambient light information; determining whether the image data matches a predetermined exposure criterion; and in response to the image data not matching the predetermined exposure criterion, obtaining the ambient light information from the sensed data; and selectively configuring a new exposure value for a plurality of imaging pixels in the image sensor to capture new image data according to the obtained ambient light information.

    PHASE LOCK LOOP
    2.
    发明申请
    PHASE LOCK LOOP 有权
    相位锁定

    公开(公告)号:US20170063385A1

    公开(公告)日:2017-03-02

    申请号:US15133369

    申请日:2016-04-20

    Applicant: MEDIATEK Inc.

    CPC classification number: H03L7/093 H03L7/085 H03L7/099 H03L7/197

    Abstract: A PLL includes a phase frequency detector (PFD), a charge pump, a capacitor coupled to the charge pump, an analog-to-digital convertor (ADC), a noise canceller, an accumulator, a loop filter, an oscillator, a digital block and a frequency divider. The PFD detects a phase difference between a reference signal and a divided signal. The charge pump generates a charge pump signal in response to the phase difference. The ADC converts the charge pump signal to a first digital signal, and quantizes it to a second digital signal. The noise canceller forms a shaped noise signal according to the first and second digital signals, and eliminates the shaped noise signal at the output of the noise canceller to generate a noise cancelled signal. The accumulator accumulates the noise cancelled signal. The loop filter filters the accumulated signal. The oscillator provides an output oscillating signal in response to the filtered signal.

    Abstract translation: PLL包括相位频率检测器(PFD),电荷泵,耦合到电荷泵的电容器,模拟 - 数字转换器(ADC),噪声消除器,累加器,环路滤波器,振荡器,数字 块和分频器。 PFD检测参考信号和分频信号之间的相位差。 电荷泵响应于相位差产生电荷泵信号。 ADC将电荷泵信号转换为第一数字信号,并将其量化为第二数字信号。 噪声消除器根据第一和第二数字信号形成成形噪声信号,并且消除噪声消除器的输出处的成形噪声信号以产生噪声消除信号。 累加器累加噪声消除信号。 环路滤波器对累积信号进行滤波。 振荡器响应于滤波信号提供输出振荡信号。

    Phase lock loop
    3.
    发明授权

    公开(公告)号:US09806725B2

    公开(公告)日:2017-10-31

    申请号:US15133369

    申请日:2016-04-20

    Applicant: MEDIATEK Inc.

    CPC classification number: H03L7/093 H03L7/085 H03L7/099 H03L7/197

    Abstract: A PLL includes a phase frequency detector (PFD), a charge pump, a capacitor coupled to the charge pump, an analog-to-digital convertor (ADC), a noise canceller, an accumulator, a loop filter, an oscillator, a digital block and a frequency divider. The PFD detects a phase difference between a reference signal and a divided signal. The charge pump generates a charge pump signal in response to the phase difference. The ADC converts the charge pump signal to a first digital signal, and quantizes it to a second digital signal. The noise canceller forms a shaped noise signal according to the first and second digital signals, and eliminates the shaped noise signal at the output of the noise canceller to generate a noise cancelled signal. The accumulator accumulates the noise cancelled signal. The loop filter filters the accumulated signal. The oscillator provides an output oscillating signal in response to the filtered signal.

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