公开(公告)号：US09899315B2

公开(公告)日：2018-02-20

申请号：US14781991

申请日：2014-04-24

Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE

Inventor： Jun Chul Kim ,  Dong Su Kim ,  Se Hoon Park ,  Jong Min Yook

IPC: H01L23/522 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/5329 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.