公开(公告)号：US11916523B2

公开(公告)日：2024-02-27

申请号：US17228982

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Wonseok Lee ,  Kent Edrian Lozada ,  Seung Tak Ryu ,  Sang Joon Kim

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F2200/129 ,  H03F2203/45512

Abstract: An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

公开(公告)号：US10680636B2

公开(公告)日：2020-06-09

申请号：US16352501

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Korea Advanced Institute of Science and Technology

Inventor： JongPal Kim ,  Ye Dam Kim ,  Seung Tak Ryu ,  Min Jae Seo ,  Dong Hwan Jin

IPC: H03M1/66 ,  H03M1/46 ,  H03M1/12

Abstract: An analog-to-digital converter (ADC) is provided. The ADC may include an input terminal configured to receive input signals, a digital-to-analog converter (DAC), a first switch configured to control a connection between the DAC and the input terminal, a comparator, a second switch configured to control a connection between the DAC and the comparator, and a controller configured to control the first switch, the second switch, the DAC and the comparator.

公开(公告)号：US10425087B1

公开(公告)日：2019-09-24

申请号：US15956335

申请日：2018-04-18

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Seung Tak Ryu ,  Woo Cheol Kim

IPC: H03K5/26 ,  H03L7/095

Abstract: The exemplary embodiments of the present disclosure relate to a phase adjustment apparatus, and its operation method, provided with a phase detector, phase controller and phase calibrator for reducing complexity of a circuit and enabling execution of a phase adjustment operation in the background.

公开(公告)号：US09318195B1

公开(公告)日：2016-04-19

申请号：US14746200

申请日：2015-06-22

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Seung Tak Ryu ,  Ji Wook Kwon ,  Dong Hwan Jin

IPC: G11C11/34 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0054

Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.

Abstract translation: 多级存储器件可以包括最高有效位（MSB）确定电路，其被配置为通过将流过存储器单元的单元电流与预定参考电流进行比较来确定多个MSB;电流/电压转换电路， 通过将单元电流复制到单元电压而获得的复制单元电流;充电时间确定电路，被配置为确定将复制的单元电流转换为单元电压并输出充电结束信号的充电时间，以及最低有效位 LSB）确定电路，被配置为根据单元电压和充电结束信号来确定多个LSB。

公开(公告)号：US10931298B2

公开(公告)日：2021-02-23

申请号：US16535761

申请日：2019-08-08

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： JongPal Kim ,  Seung Tak Ryu ,  Min Jae Seo

IPC: H03M1/46 ,  H03M1/12

Abstract: An analog-to-digital converter includes an input buffer connected to an input terminal receiving an input signal through a first sampling switch, a comparator connected to the input buffer, a sampling capacitor connected between the input buffer and the comparator, and connected to a second sampling switch, a digital-to-analog converter connected to the comparator, and a controller, connected between the comparator and the digital-to-analog converter, configured to output a signal to the digital-to-analog converter based on the comparator.

公开(公告)号：US09159411B2

公开(公告)日：2015-10-13

申请号：US13935407

申请日：2013-07-03

Applicant: SK HYNIX INC. ,  Korea Advanced Institute of Science and Technology

Inventor： Chul Hyun Park ,  Seung Tak Ryu ,  Ji Wook Kwon ,  Dong Hwan Jin

IPC: G11C7/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2213/72

Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.

Abstract translation: 多级存储装置包括被配置为传递具有不同级别的电流的两个或更多个电流路径，选择性地耦合到两个或更多个电流路径的存储器单元，以及单元电流复制单元，被配置为复制流过存储器单元的单元电流 。