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公开(公告)号：US09159411B2
公开(公告)日：2015-10-13
申请号：US13935407
申请日：2013-07-03
Inventor： Chul Hyun Park , Seung Tak Ryu , Ji Wook Kwon , Dong Hwan Jin
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C2013/0042 , G11C2013/0054 , G11C2213/72
Abstract: A multi-level memory apparatus includes two or more current paths configured to pass currents having different levels, a memory cell selectively coupled to the two or more current paths, and a cell current copy unit configured to copy a cell current flowing through the memory cell.
Abstract translation: 多级存储装置包括被配置为传递具有不同级别的电流的两个或更多个电流路径，选择性地耦合到两个或更多个电流路径的存储器单元，以及单元电流复制单元，被配置为复制流过存储器单元的单元电流 。
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公开(公告)号：US09318195B1
公开(公告)日：2016-04-19
申请号：US14746200
申请日：2015-06-22
Inventor： Seung Tak Ryu , Ji Wook Kwon , Dong Hwan Jin
CPC classification number: G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0061 , G11C2013/0054
Abstract: A multi-level memory device may include a most significant bit (MSB) determination circuit configured to determine a plurality of MSBs by comparing a cell current flowing through a memory cell with a predetermined reference current, a current/voltage conversion circuit configured to convert a copied cell current obtained by copying the cell current into a cell voltage, a charging time determination circuit configured to determine a charging time during which the copied cell current is converted into the cell voltage and output a charging end signal, and a least significant bit (LSB) determination circuit configured to determine a plurality of LSBs according to the cell voltage and the charging end signal.
Abstract translation: 多级存储器件可以包括最高有效位（MSB）确定电路，其被配置为通过将流过存储器单元的单元电流与预定参考电流进行比较来确定多个MSB;电流/电压转换电路， 通过将单元电流复制到单元电压而获得的复制单元电流;充电时间确定电路，被配置为确定将复制的单元电流转换为单元电压并输出充电结束信号的充电时间，以及最低有效位 LSB）确定电路，被配置为根据单元电压和充电结束信号来确定多个LSB。
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