知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.043 seconds)

    VERIFICATION OF A HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT TO IMPLEMENT A FLOATING POINT PRODUCT OF POWER FUNCTIONS
    1.
    发明公开
    VERIFICATION OF A HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT TO IMPLEMENT A FLOATING POINT PRODUCT OF POWER FUNCTIONS 审中-公开

    公开(公告)号：US20240126965A1

    公开(公告)日：2024-04-18

    申请号：US18216196

    申请日：2023-06-29

    Applicant: Imagination Technologies Limited

    Inventor： Rachel Edmonds ,  Sam Elliott ,  Simon Gaulter

    IPC: G06F30/33 ,  G06F7/499

    CPC classification number: G06F30/33 ,  G06F7/49915

    Abstract: Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t0× . . . ×xntn, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X′ and Y′ with a same mantissa and X′exp−(t0X0.exp+ . . . +tnXn.exp)=Y′exp−(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer.

    VERIFICATION OF HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT THAT IMPLEMENTS A FUNCTION THAT IS POLYNOMIAL IN ONE OR MORE SUB-FUNCTIONS
    2.
    发明申请
    VERIFICATION OF HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT THAT IMPLEMENTS A FUNCTION THAT IS POLYNOMIAL IN ONE OR MORE SUB-FUNCTIONS 有权

    公开(公告)号：US20220147677A1

    公开(公告)日：2022-05-12

    申请号：US17501666

    申请日：2021-10-14

    Applicant: Imagination Technologies Limited

    Inventor： Rachel Edmonds ,  Sam Elliott

    IPC: G06F30/3323

    Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

    VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION
    4.
    发明申请
    VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION 有权

    公开(公告)号：US20230097314A1

    公开(公告)日：2023-03-30

    申请号：US18076338

    申请日：2022-12-06

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott ,  Rachel Edmonds

    IPC: G06F30/3323

    Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

    Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more sub-functions
    5.
    发明授权
    Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more sub-functions 有权

    公开(公告)号：US12190035B2

    公开(公告)日：2025-01-07

    申请号：US17501666

    申请日：2021-10-14

    Applicant: Imagination Technologies Limited

    Inventor： Rachel Edmonds ,  Sam Elliott

    IPC: G06F30/3323 ,  G06F119/16

    Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.

    Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination
    6.
    发明授权
    Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination 有权

    公开(公告)号：US11531800B2

    公开(公告)日：2022-12-20

    申请号：US17501219

    申请日：2021-10-14

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott ,  Rachel Edmonds

    IPC: G06F30/3323 ,  G06F30/392 ,  G06F111/04

    Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

    VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION
    7.
    发明申请
    VERIFICATION OF HARDWARE DESIGN FOR COMPONENT THAT EVALUATES AN ALGEBRAIC EXPRESSION USING DECOMPOSITION AND RECOMBINATION 有权

    公开(公告)号：US20220114315A1

    公开(公告)日：2022-04-14

    申请号：US17501219

    申请日：2021-10-14

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott ,  Rachel Edmonds

    IPC: G06F30/3323

    Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

Patent Agency Ranking