Method for forming MRAM bit having a bottom sense layer utilizing electroless plating

    公开(公告)号:US06716644B2

    公开(公告)日:2004-04-06

    申请号:US10146890

    申请日:2002-05-17

    CPC classification number: H01L27/222 H01L43/12

    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

    Magnetoresistive memory device assemblies

    公开(公告)号:US07038286B2

    公开(公告)日:2006-05-02

    申请号:US10920740

    申请日:2004-08-17

    CPC classification number: H01L27/222

    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

    Methods of forming magnetoresistive memory device assemblies

    公开(公告)号:US06780653B2

    公开(公告)日:2004-08-24

    申请号:US10165352

    申请日:2002-06-06

    CPC classification number: H01L27/222

    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

    Method for forming MRAM bit having a bottom sense layer utilizing electroless plating
    4.
    发明授权
    Method for forming MRAM bit having a bottom sense layer utilizing electroless plating 有权
    用于形成具有利用无电镀的底部感测层的MRAM钻头的方法

    公开(公告)号:US07547559B2

    公开(公告)日:2009-06-16

    申请号:US11657725

    申请日:2007-01-25

    CPC classification number: H01L27/222 H01L43/12

    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

    Abstract translation: 本发明提供一种形成MRAM单元的方法,该方法在制造期间使电短路的发生最小化。 沟槽中的第一导体设置在绝缘层中,并且绝缘层和第一导体的上表面被平坦化。 然后,电介质层被沉积成稍大于稍后形成的感应层的期望最终厚度的厚度。 然后对电介质层进行图案化和蚀刻,以形成第一导体上的电池形状的开口。 然后,将坡莫合金电镀在电池形状中以形成感测层。 感应层和电介质层被平坦化,然后沉积非磁性隧道势垒层。 最后,在隧道势垒层上方形成钉扎层。

    Process flow for building MRAM structures
    5.
    发明授权
    Process flow for building MRAM structures 有权
    构建MRAM结构的流程

    公开(公告)号:US07306954B2

    公开(公告)日:2007-12-11

    申请号:US10637096

    申请日:2003-08-08

    CPC classification number: H01L27/222 G11C11/15 H01L43/08 H01L43/12

    Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

    Abstract translation: MRAM结构采用分层磁性和非磁性材料的磁性来读取存储器存储逻辑状态。 可以通过改变分层磁堆栈结构的形状来实现开关可靠性的改进。 在沉积分层磁堆栈结构之前,在ILD层中形成具有倾斜内壁的凹陷区域通过允许使用CMP工艺来定义磁头形状而产生比现有技术更大的优点。 凹陷区域的倾斜内壁,对于本发明而言是单一的,提供了磁性堆叠结构的独特的形成和成形,这可以减小磁性堆叠结构的磁性层之间的磁耦合效应。

    Methods of forming magnetoresistive memory device assemblies
    6.
    发明授权
    Methods of forming magnetoresistive memory device assemblies 有权
    形成磁阻存储器件组件的方法

    公开(公告)号:US06780654B2

    公开(公告)日:2004-08-24

    申请号:US10321165

    申请日:2002-12-16

    CPC classification number: H01L27/222

    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

    Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上,并被图案化成多条线。 这些线与MRAM器件一一对应,并且彼此间隔开。 在将导电材料图案化成线之后,形成磁性材料以在线之间和线之间的空间内延伸。

    MRAM memory cell having an electroplated bottom layer
    7.
    发明授权
    MRAM memory cell having an electroplated bottom layer 有权
    具有电镀底层的MRAM存储单元

    公开(公告)号:US07183621B2

    公开(公告)日:2007-02-27

    申请号:US10761247

    申请日:2004-01-22

    CPC classification number: H01L27/222 H01L43/12

    Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

    Abstract translation: 本发明提供一种形成MRAM单元的方法,该方法在制造期间使电短路的发生最小化。 沟槽中的第一导体设置在绝缘层中,并且绝缘层和第一导体的上表面被平坦化。 然后,电介质层被沉积成稍大于稍后形成的感应层的期望最终厚度的厚度。 然后对电介质层进行图案化和蚀刻,以形成第一导体上的电池形状的开口。 然后,将坡莫合金电镀在电池形状中以形成感测层。 感应层和电介质层被平坦化,然后沉积非磁性隧道势垒层。 最后,在隧道势垒层上方形成钉扎层。

    Magnetoresistive memory device assemblies
    8.
    发明授权
    Magnetoresistive memory device assemblies 有权
    磁阻存储器件组件

    公开(公告)号:US06781174B2

    公开(公告)日:2004-08-24

    申请号:US10302187

    申请日:2002-11-21

    CPC classification number: H01L27/222

    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

    Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上,并被图案化成多条线。 这些线与MRAM器件一一对应,并且彼此间隔开。 在将导电材料图案化成线之后,形成磁性材料以在线之间和线之间的空间内延伸。

    Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies
    9.
    发明授权
    Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies 有权
    磁阻存储器件组件,以及形成磁阻存储器件组件的方法

    公开(公告)号:US07279762B2

    公开(公告)日:2007-10-09

    申请号:US11295177

    申请日:2005-12-05

    CPC classification number: H01L27/222

    Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

    Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上,并被图案化成多条线。 这些线与MRAM器件一一对应,并且彼此间隔开。 在将导电材料图案化成线之后,形成磁性材料以在线之间和线之间的空间内延伸。

    Process flow for building MRAM structures
    10.
    发明授权
    Process flow for building MRAM structures 有权
    构建MRAM结构的流程

    公开(公告)号:US06828639B2

    公开(公告)日:2004-12-07

    申请号:US10198194

    申请日:2002-07-17

    CPC classification number: H01L27/222 G11C11/15 H01L43/08 H01L43/12

    Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

    Abstract translation: MRAM结构采用分层磁性和非磁性材料的磁性来读取存储器存储逻辑状态。 可以通过改变分层磁堆栈结构的形状来实现开关可靠性的改进。 在沉积分层磁堆栈结构之前,在ILD层中形成具有倾斜内壁的凹陷区域通过允许使用CMP工艺来定义磁头形状而产生比现有技术更大的优点。 凹陷区域的倾斜内壁,对于本发明而言是单一的,提供了磁性堆叠结构的独特的形成和成形,这可以减小磁性堆叠结构的磁性层之间的磁耦合效应。

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