公开(公告)号：US12183425B2

公开(公告)日：2024-12-31

申请号：US17893067

申请日：2022-08-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huifang Jiao ,  Ran He ,  Luming Fan ,  Yue Pan

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08

Abstract: A memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an ith column are connected to an ith local bitline, the ith local bitline is connected to an ith global bitline by using an ith bitline switch in the N bitline switches. A memory array is fine-grained, so that ith local bitlines in the S storage blocks can share one global bitline.

公开(公告)号：US20230352552A1

公开(公告)日：2023-11-02

申请号：US18350348

申请日：2023-07-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Luming Fan ,  Yanxiang Liu ,  Jeffrey Junhao Xu ,  Francis Lionel Benistant ,  Zhaozhao Hou

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/66545

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.