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公开(公告)号：US20180330466A1
公开(公告)日：2018-11-15
申请号：US15595289
申请日：2017-05-15
Applicant: Google Inc.
Inventor： Fabrizio Basso , Edward Chang , Daniel Finchelstein , Timothy Knight , William Mark , Albert Meixner , Shahriar Rabii , Jason Redgrave , Masumi Reynders , Ofer Shacham , Don Stark , Michelle Tomasko
CPC classification number: G06T1/20 , G06K9/00221 , G06K9/00335 , G06K9/00624 , G06T3/4015 , H04N5/217 , H04N5/23232 , H04N5/23267
Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.
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公开(公告)号：US20170256021A1
公开(公告)日：2017-09-07
申请号：US15599348
申请日：2017-05-18
Applicant: Google Inc.
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US20180005347A1
公开(公告)日：2018-01-04
申请号：US15598082
申请日：2017-05-17
Applicant: Google Inc.
Inventor： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William Mark , Jason Rupert Redgrave , Ofer Shacham
CPC classification number: G06T1/20 , G06K9/00986 , G11C19/28
Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
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公开(公告)号：US20170256230A1
公开(公告)日：2017-09-07
申请号：US15599086
申请日：2017-05-18
Applicant: Google Inc.
Inventor： Albert Meixner , Neeti Desai , Dilan Manatunga , Jason Rupert Redgrave , William Mark
CPC classification number: G09G5/006 , G06F12/06 , G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/02 , G09G2340/02 , H04N1/32358 , H04N2201/3291
Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.
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