公开(公告)号：US20150026385A1

公开(公告)日：2015-01-22

申请号：US14315099

申请日：2014-06-25

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Robert LASATER ,  Thomas BOYLE ,  John PETERS ,  Guangyu SHI

IPC: G06F9/50 ,  G06F13/16

CPC classification number: G06F13/161 ,  G06F9/5005 ,  G06F13/4036 ,  H04L47/785

Abstract: Embodiments of the present invention provide a solution for managing inter-domain resource allocation in a Peripheral Component Interconnect-Express (PCIe) network. One processor among a plurality of link processors is elected as a management processor. The management processor obtains information about available resources of PCIe network. When a resource request from a request processor is received, the management processor allocates a resource of the available resources to the requesting processor. The management processor instructs one or more link processors to program one or more inter-domain NTBs through which the traffic between the allocated resource and the requesting processor is going to flow according to the memory address information of the allocated resource, to allow cross-domain resource access between the requesting processor and the allocated resource.

Abstract translation: 本发明的实施例提供了一种用于管理外围组件互连Express（PCIe）网络中的域间资源分配的解决方案。 多个链接处理器中的一个处理器被选为管理处理器。 管理处理器获取有关PCIe网络可用资源的信息。 当接收到来自请求处理器的资源请求时，管理处理器将可用资源的资源分配给请求处理器。 管理处理器指示一个或多个链路处理器对一个或多个域间NTB进行编程，根据所分配的资源的存储器地址信息，分配的资源和请求处理器之间的流量将通过该NTB进行编程，以允许跨域 请求处理器和分配的资源之间的资源访问。

公开(公告)号：US20180157614A1

公开(公告)日：2018-06-07

申请号：US15885398

申请日：2018-01-31

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Guangyu SHI

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0026

Abstract: A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message.

公开(公告)号：US20160352651A1

公开(公告)日：2016-12-01

申请号：US15236636

申请日：2016-08-15

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Robert LASATER ,  Guangyu SHI ,  Thomas BOYLE

IPC: H04L12/947 ,  H04L12/707 ,  H04L12/933 ,  H04L12/24

CPC classification number: H04L49/25 ,  H04L12/4015 ,  H04L12/4625 ,  H04L41/12 ,  H04L45/24 ,  H04L45/48 ,  H04L49/15

Abstract: In a high-dimensional PCI-Express (PCIe) network, implementation of alternative paths is accomplished to facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. Different portions of the PCIe tree structure are connected to allow a shorter path for communications by utilizing a bridge circuit configured as an end-point with respect to two switches that are not directly connected in the PCIe tree topology. The bridge circuit performs address translations to allow communications from one switch to be passed via the bridge circuit to the other switch.

Abstract translation: 在高维PCI-Express（PCIe）网络中，实现替代路径可实现灵活的拓扑实现和网络域缩放，同时实现改进的通信延迟。 连接PCIe树结构的不同部分以通过利用被配置为在PCIe树拓扑中未直接连接的两个交换机的端点的桥接电路来允许通信的较短路径。 桥接电路执行地址转换以允许来自一个开关的通信通过桥接电路传递到另一个开关。

公开(公告)号：US20160378706A1

公开(公告)日：2016-12-29

申请号：US14753400

申请日：2015-06-29

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Thomas BOYLE ,  Guangyu SHI

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4022 ,  G06F13/404

Abstract: A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.

Abstract translation: 外围组件互连表示具有用于（a）向PCI-e拓扑树分配地址的处理器的PCI-e网络系统，包括：以给定级别和宽度方向遍历向下连接到互连的下行链路耦合; 在水平上确定哪个下行链路耦合连接到节点; 在所述级别向所确定的具有节点的下行链路耦合的节点分配地址; 并且（b）传播一个级别，包括：在水平和深度方向上遍历下行链路耦合到PCI-e网络的互连，在该级别确定哪个下行链路耦合耦合到 沿深度方向连续进行深度方向的其他互连，下一个互连的下行链路耦合的下一级; 并且或者重复（a）和（b）直到节点被分配在PCI-e树拓扑网络内的地址。

公开(公告)号：US09465760B2

公开(公告)日：2016-10-11

申请号：US14083206

申请日：2013-11-18

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Robert Lasater ,  Thomas Boyle ,  John Peters ,  Guangyu Shi

IPC: G06F13/00 ,  G06F13/32 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/32 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract translation: 一种用于初始化的设备。 该装置包括用于管理耦合到PCI-Express（PCIe）结构的多个I / O设备的初始化的管理I / O设备控制器。 管理I / O设备控制器被配置为接收注册第一工作者计算资源的目标中断寄存器地址的请求，其中目标中断寄存器地址与由耦合到第一工作计算资源的第一I / O设备产生的第一中断相关联 PCIe面料。 管理I / O设备控制器的映射模块被配置为将目标中断寄存器地址映射到第一I / O设备所在的域的映射中断寄存器地址。 翻译中断寄存器表包括与多个工作人员计算资源的多个目标中断寄存器地址相关联的域中的多个映射的中断寄存器地址。

公开(公告)号：US20160188643A1

公开(公告)日：2016-06-30

申请号：US14588033

申请日：2014-12-31

Applicant: Futurewei Technologies, Inc.

Inventor： Yan SUN ,  Norbert EGI ,  Edward CHING

IPC: G06F17/30

CPC classification number: G06F7/22 ,  G06F7/06

Abstract: Embodiments of the present invention pertain to a method and apparatus for a scalable sorting of a data set in a database on a computer system. A number of contiguous ranges spanning the data set are defined. Each individual data value of the data set is assigned to a range to which it falls into. The values in the ranges are then sorted. The sorting can be performed by different nodes in parallel. Once the sorting is completed, the results are stored in contiguous memory locations. This results the overall data set being sorted.

Abstract translation: 本发明的实施例涉及用于在计算机系统上的数据库中的数据集的可伸缩分类的方法和装置。 定义跨越数据集的多个连续范围。 将数据集的每个单独的数据值分配给它所属的范围。 然后对范围中的值进行排序。 排序可以由不同的节点并行执行。 排序完成后，结果将存储在连续的内存位置。 这导致整个数据集被排序。

公开(公告)号：US20150143016A1

公开(公告)日：2015-05-21

申请号：US14083206

申请日：2013-11-18

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Robert LASATER ,  Thomas BOYLE ,  John PETERS ,  Guangyu SHI

IPC: G06F13/32 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/32 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract translation: 一种用于初始化的设备。 该装置包括用于管理耦合到PCI-Express（PCIe）结构的多个I / O设备的初始化的管理I / O设备控制器。 管理I / O设备控制器被配置为接收注册第一工作者计算资源的目标中断寄存器地址的请求，其中目标中断寄存器地址与由耦合到第一工作计算资源的第一I / O设备产生的第一中断相关联 PCIe面料。 管理I / O设备控制器的映射模块被配置为将目标中断寄存器地址映射到第一I / O设备所在的域的映射中断寄存器地址。 翻译中断寄存器表包括与多个工作人员计算资源的多个目标中断寄存器地址相关联的域中的多个映射的中断寄存器地址。

公开(公告)号：US20170024340A1

公开(公告)日：2017-01-26

申请号：US15287985

申请日：2016-10-07

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Robert LASATER ,  Thomas BOYLE ,  John PETERS ,  Guangyu SHI

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/24 ,  G06F13/32 ,  G06F13/404 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources.

Abstract translation: 一种用于初始化的设备。 该装置包括用于管理耦合到PCI-Express（PCIe）结构的多个I / O设备的初始化的管理I / O设备控制器。 管理I / O设备控制器被配置为接收注册第一工作者计算资源的目标中断寄存器地址的请求，其中目标中断寄存器地址与由耦合到第一工作计算资源的第一I / O设备产生的第一中断相关联 PCIe面料。 管理I / O设备控制器的映射模块被配置为将目标中断寄存器地址映射到第一I / O设备所在的域的映射中断寄存器地址。 翻译中断寄存器表包括与多个工作人员计算资源的多个目标中断寄存器地址相关联的域中的多个映射中断寄存器地址。

公开(公告)号：US20160292101A1

公开(公告)日：2016-10-06

申请号：US14678528

申请日：2015-04-03

Applicant: Futurewei Technologies, Inc.

Inventor： Norbert EGI ,  Guangyu SHI

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4282

Abstract: Systems and methods for offloading computations from a CPU directly to an accelerator engine are disclosed. One embodiment includes determining a function of an application to be offloaded from a CPU to an accelerator engine, locating data within a file necessary to perform the functions, programming a logic of the accelerator engine based on the function to be offloaded, programming a DMA engine to move a copy the data from a secondary storage device to the accelerator engine, and processing the data at the accelerator engine using the programmed logic.

Abstract translation: 公开了将计算从CPU直接卸载到加速器引擎的系统和方法。 一个实施例包括确定要从CPU卸载到加速器引擎的应用的功能，将执行功能所需的文件中的数据定位，基于要卸载的功能对加速器引擎的逻辑进行编程，编程DMA引擎 将数据从辅助存储设备复制到加速器引擎，并使用编程逻辑在加速器引擎处理数据。

公开(公告)号：US20160124864A1

公开(公告)日：2016-05-05

申请号：US14532874

申请日：2014-11-04

Applicant: Futurewei Technologies, Inc.

Inventor： Yan SUN ,  Norbert EGI

IPC: G06F12/10

CPC classification number: G06F12/1018 ,  G06F12/0864 ,  G06F17/30949

Abstract: Methods and apparatuses for insertion, searching, deletion, and load balancing using a hierarchical series of hash tables are described herein. The techniques disclosed provide nearly collision free or deterministic hash functions using a bitmap as a pre-filter. The hash functions have different priorities and one hashing result will be used to perform main memory access. For the hash functions, two hash bitmaps are used to store valid data and collision information. There is no collision allowed in the hash tables except for the hash table with the lowest priority. The hash tables and bitmaps may be stored in one or more caches in (e.g., a cache of a CPU, Block RAMs in FPGAs, etc.) which perform much faster than main memory.

Abstract translation: 这里描述了使用分级序列的散列表来插入，搜索，删除和负载平衡的方法和装置。 所公开的技术使用位图作为前置滤波器提供了几乎无冲突的或确定性的散列函数。 哈希函数具有不同的优先级，一个散列结果将用于执行主内存访问。 对于哈希函数，使用两个哈希位图来存储有效的数据和冲突信息。 散列表中不存在冲突，除了优先级最低的哈希表外。 散列表和位图可以存储在执行比主存储器快得多的（例如，CPU的高速缓存，FPGA中的块RAM等）中的一个或多个高速缓存中。