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    HIERARCHICAL MEMORY SYSTEM COMPILER
    3.
    发明申请
    HIERARCHICAL MEMORY SYSTEM COMPILER 有权
    分层存储系统编译器

    公开(公告)号：US20160179394A1

    公开(公告)日：2016-06-23

    申请号：US14083437

    申请日：2013-11-18

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

    IPC: G06F3/06

    CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

    Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

    Abstract translation: 为集成电路设计存储器子系统可能是耗时且昂贵的任务。 为了减少开发时间和成本，公开了一种用于设计和构建高速存储器操作的自动化系统和方法。 自动化系统接受一组期望的存储特性，然后有选择地选择不同的潜在存储器系统设计类型和每种存储器系统设计类型的不同实现。 潜在的存储器系统设计类型可以包括传统的存储器系统，优化的传统存储器系统，智能存储器系统和分层存储器系统。 满足所指定的所需存储器特性集合的一组选定的存储器系统被输出到电路设计者。 当电路设计者选择所提出的存储器系统时，自动化系统产生完整的存储器系统设计，存储器系统的模型以及用于存储器系统的测试套件。

    METHODS AND APPARATUS FOR TESTING AND REPAIRING DIGITAL MEMORY CIRCUITS
    4.
    发明申请
    METHODS AND APPARATUS FOR TESTING AND REPAIRING DIGITAL MEMORY CIRCUITS 审中-公开
    用于测试和修复数字存储器电路的方法和装置

    公开(公告)号：US20160005493A1

    公开(公告)日：2016-01-07

    申请号：US14856758

    申请日：2015-09-17

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Shadab Nazar ,  Sanjeev Joshi

    IPC: G11C29/12

    CPC classification number: G11C29/12 ,  G11C29/08 ,  G11C29/56008 ,  G11C29/70 ,  G11C2029/0401 ,  G11C2029/0409

    Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.

    Abstract translation: 公开了用于存储器的ActiveTest解决方案，其可以在包含数字存储器的产品的操作期间搜索存储器错误。 ActiveTest系统测试正常内存用户未被访问的内存块，以便在后台持续测试内存系统。 当ActiveTest系统和内存用户之间存在冲突时，内存用户通常被优先考虑。

    TOPOLOGY EXPLORER
    6.
    发明申请
    TOPOLOGY EXPLORER 审中-公开

    公开(公告)号：US20180367412A1

    公开(公告)日：2018-12-20

    申请号：US15790577

    申请日：2017-10-23

    Applicant: Cisco Technology, Inc.

    Inventor： Divjyot Sethi ,  Chandra Nagarajan ,  Ramana Rao Kompella ,  Gaurav Gupta ,  Sundar Iyer

    IPC: H04L12/24

    Abstract: Systems, methods, and computer-readable media for discovering a network's topology and health. In some examples, a system can obtain, from at least one of a plurality of controllers on a network, a logical model of the network, the logical model including configurations of one or more objects defined for the network. Based on the logical model, the system can identify a respective location of the plurality of controllers in the network and a plurality of nodes in a fabric of the network. Based on the respective location of the plurality of controllers and plurality of nodes, the system can poll the plurality of controllers and plurality of nodes for respective status information, and determine a health and topology of the network based on the logical model, the respective location, and respective status information.

    STATIC NETWORK POLICY ANALYSIS FOR NETWORKS
    7.
    发明申请
    STATIC NETWORK POLICY ANALYSIS FOR NETWORKS 审中-公开

    公开(公告)号：US20180309629A1

    公开(公告)日：2018-10-25

    申请号：US15663598

    申请日：2017-07-28

    Applicant: Cisco Technology, Inc.

    Inventor： Kartik Mohanram ,  Chandra Nagarajan ,  Sundar Iyer ,  Shadab Nazar ,  Ramana Rao Kompella

    IPC: H04L12/24 ,  H04L12/26

    Abstract: Systems, methods, and computer-readable media for static network policy analysis for a network. In one example, a system obtains a logical model based on configuration data stored in a controller on a software-defined network, the logical model including a declarative representation of respective configurations of objects in the software-defined network, the objects including one or more endpoint groups, bridge domains, contexts, or tenants. The system defines rules representing respective conditions of the objects according to a specification corresponding to the software-defined network, and determines whether the respective configuration of each of the objects in the logical model violates one or more of the rules associated with that object. When the respective configuration of an object in the logical model violates one or more of the rules, the system detects an error in the respective configuration associated with that object.

    High speed memory systems and methods for designing hierarchical memory systems
    8.
    发明授权
    High speed memory systems and methods for designing hierarchical memory systems 有权

    公开(公告)号：US10042573B2

    公开(公告)日：2018-08-07

    申请号：US15213492

    申请日：2016-07-19

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Shang-Tse Chuang

    IPC: G06F12/02 ,  G06F3/06 ,  G06F12/08

    Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

    HIGH SPEED MEMORY SYSTEMS AND METHODS FOR DESIGNING HIERARCHICAL MEMORY SYSTEMS
    9.
    发明申请
    HIGH SPEED MEMORY SYSTEMS AND METHODS FOR DESIGNING HIERARCHICAL MEMORY SYSTEMS 审中-公开
    高速存储器系统和设计分层存储器系统的方法

    公开(公告)号：US20160328170A1

    公开(公告)日：2016-11-10

    申请号：US15213492

    申请日：2016-07-19

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Shang-Tse Chuang

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/254

    Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

    Abstract translation: 公开了一种用于设计和构造分层存储器系统的系统和方法。 公开了多种不同的算法存储器块。 每个算法存储器块包括实现特定存储算法和一组较低级存储器组件的存储器控​​制器。 这些较低级存储器组件中的每一个可以用另一个算法存储器块或基本存储器块来构造。 通过在各种不同的分层组织中组织算法存储器块，可以创建提供新特征的不同复杂的存储器系统。

    System and Method for Simultaneously Storing and Reading Data from a Memory System
    10.
    发明申请
    System and Method for Simultaneously Storing and Reading Data from a Memory System 审中-公开
    从存储系统同时存储和读取数据的系统和方法

    公开(公告)号：US20150339227A1

    公开(公告)日：2015-11-26

    申请号：US14730696

    申请日：2015-06-04

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Shang-Tse Chuang

    IPC: G06F12/02 ,  G06F12/06

    CPC classification number: G06F12/0292 ,  G06F12/06 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/502 ,  G06F2212/657

    Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. This allows the memory system to both store and read data in the same cycle with no conflicts.

    Abstract translation: 公开了一种用于提供高速存储器操作的系统和方法。 该技术使用虚拟化的存储器空间将虚拟地址空间映射到更大的物理地址空间，其中不会发生存储体冲突。 更大的物理地址空间用于通过将正在写入存储器的数据的虚拟存储器地址移动到物理存储器中的不同位置来消除存储器组冲突而发生存储器组冲突。 这允许存储器系统在相同周期内存储和读取数据，而不会发生冲突。

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