公开(公告)号：US11894296B2

公开(公告)日：2024-02-06

申请号：US17446729

申请日：2021-09-02

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  Tomer Osi ,  Amendra Koul ,  David Nozadze ,  Upendranadh R. Kareti ,  Joel R. Goergen

IPC: H01L23/50 ,  H01L23/367 ,  H01L23/498 ,  H05K7/20

CPC classification number: H01L23/50 ,  H01L23/3672 ,  H01L23/49838 ,  H05K7/209

Abstract: An apparatus includes an integrated circuit package and a heatsink. The integrated circuit package includes a substrate, an integrated circuit, a first plurality of signal conductors, and a second plurality of signal conductors. The substrate includes a first surface and a second surface opposite the first surface. The integrated circuit is coupled to the first surface of the substrate. The first plurality of signal conductors are arranged along a periphery of the first surface of the substrate. The second plurality of signal conductors are arranged along a periphery of the second surface of the substrate. The heatsink includes a first portion positioned along the first surface of the substrate and a second portion positioned along the second surface of the substrate.

公开(公告)号：US11777239B2

公开(公告)日：2023-10-03

申请号：US17653466

申请日：2022-03-04

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  Tomer Osi ,  Amendra Koul ,  David Nozadze ,  Upendranadh R. Kareti ,  Joel R. Goergen

IPC: H01R12/75 ,  H01R12/72

CPC classification number: H01R12/727 ,  H01R12/75

Abstract: Certain aspects of the present disclosure provide techniques for pinless interconnect for twinaxial cables to an IC. This includes a socket coupled to an integrated circuit (IC), a port structure coupled to the socket, and a ground connector inserted into the port structure. It further includes a twinaxial cable including a pair of conductors inserted through the ground connector to establish an electrical connection between the twinaxial cable and the IC.

公开(公告)号：US12142578B2

公开(公告)日：2024-11-12

申请号：US17492836

申请日：2021-10-04

Applicant: Cisco Technology, Inc.

Inventor： Xiaohong Wu ,  Xing Wang ,  Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  Tomer Osi ,  Joel Goergen

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/053 ,  H01R12/00 ,  H05K1/18 ,  H05K7/10

Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.

公开(公告)号：US20230397343A1

公开(公告)日：2023-12-07

申请号：US17942711

申请日：2022-09-12

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Sayed Ashraf Mamun ,  D. Brice Achkir ,  David Nozadze ,  Amendra Koul ,  Upen Reddy Kareti

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4697 ,  H05K3/0047

Abstract: The techniques described herein relate to an apparatus including: a support structure of an integrated circuit device; and an elongated cavity formed in the support structure of the integrated circuit device, wherein an interior of the elongated cavity is plated with a conductive material separated into a first power connection portion and a first ground connection portion.

公开(公告)号：US20250031300A1

公开(公告)日：2025-01-23

申请号：US18451477

申请日：2023-08-17

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Amendra Koul ,  David Nozadze ,  Joel Richard Goergen ,  Upen Reddy Kareti ,  Sayed Ashraf Mamun

IPC: H05K1/02

Abstract: Provide for herein is an apparatus that includes multiple printed circuit board (PCB) layers and a via assembly. The via assembly includes a signal via extending through the multiple layers, and the signal via is configured to transmit a signal between the layers. The via assembly also includes a capacitive structure connected to the signal via to adjust an impedance of the via assembly along the via assembly. The capacitive structure is physically and electrically separate from other components of the PCB.

公开(公告)号：US20250029931A1

公开(公告)日：2025-01-23

申请号：US18453720

申请日：2023-08-22

Applicant: Cisco Technology, Inc.

Inventor： Mike Sapozhnikov ,  Amendra Koul ,  David Nozadze ,  Joel Richard Goergen ,  Sayed Ashraf Mamun ,  Srinath Penugonda

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

Abstract: In some embodiments, an integrated circuit (IC) includes multiple packages that are separate from one another. Each package includes a pad, and a core via is electrically coupled to the pads of the separate packages to electrically couple the packages to one another. At least one of the pads includes an oblong shape to match its impedance with the impedance of the core via.

公开(公告)号：US20240356251A1

公开(公告)日：2024-10-24

申请号：US18455803

申请日：2023-08-25

Applicant: Cisco Technology, Inc.

Inventor： David Nozadze ,  Mike Sapozhnikov ,  Amendra Koul ,  Sayed Ashraf Mamun ,  Upen Reddy Kareti

IPC: H01R12/53 ,  H01R12/55 ,  H05K1/14

CPC classification number: H01R12/53 ,  H01R12/55 ,  H05K1/144 ,  H01R43/007 ,  H05K1/0219 ,  H05K2201/0314 ,  H05K2201/041 ,  H05K2201/10356

Abstract: In some aspects, the techniques described herein relate to an apparatus for connecting cables to Input Output (IO) connector pins, including: a first Printed Circuit Board (PCB) configured to receive terminal ends of a plurality of cables, wherein the terminal ends of the plurality of cables are electrically isolated from one another in the first PCB; a second PCB configured to receive a plurality of IO connector pins, wherein the plurality of IO connector pins are electrically isolated from one another in the second PCB; and wherein the first PCB is configured to join to the second PCB to connect each of the terminal ends of the plurality of cables to corresponding pins of the plurality of IO connector pins.