公开(公告)号：US11269529B2

公开(公告)日：2022-03-08

申请号：US16893044

申请日：2020-06-04

Applicant: Beijing Baidu Netcom Science and Technology Co., Ltd.

Inventor： Haoyang Li ,  Yuan Ruan ,  Yupeng Li

IPC: G06F9/02 ,  G06F3/06 ,  G06F13/28 ,  G06N3/08 ,  G06F9/38

Abstract: A neural network data processing apparatus includes: an instruction parsing module, configured to split a DMA task into multiple subtasks and acquire configuration information of a data sub-block corresponding to each subtask, where the subtasks are in a one-to-one correspondence with data sub-blocks of transported neural network data; a data reading module, configured to read a first data sub-block according to the configuration information, where the first data sub-block is a data sub-block among data sub-blocks corresponding to multiple subtasks; a data processing module, configured to compress the first data sub-block; a data write-out module, configured to output compressed data resulting from the compression of the first data sub-block.

公开(公告)号：US20210200437A1

公开(公告)日：2021-07-01

申请号：US16893044

申请日：2020-06-04

Applicant: Beijing Baidu Netcom Science and Technology Co., Ltd.

Inventor： Haoyang Li ,  Yuan Ruan ,  Yupeng Li

IPC: G06F3/06 ,  G06F13/28 ,  G06N3/08

Abstract: A neural network data processing apparatus includes: an instruction parsing module, configured to split a DMA task into multiple subtasks and acquire configuration information of a data sub-block corresponding to each subtask, where the subtasks are in a one-to-one correspondence with data sub-blocks of transported neural network data; a data reading module, configured to read a first data sub-block according to the configuration information, where the first data sub-block is a data sub-block among data sub-blocks corresponding to multiple subtasks; a data processing module, configured to compress the first data sub-block; a data write-out module, configured to output compressed data resulting from the compression of the first data sub-block.

公开(公告)号：US20200050450A1

公开(公告)日：2020-02-13

申请号：US16458381

申请日：2019-07-01

Applicant: Beijing Baidu Netcom Science and Technology Co., Ltd.

Inventor： Jing Wang ,  Wei Qi ,  Yupeng Li ,  Xiaozhang Gong

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/46

Abstract: Embodiments of the present disclosure relate to a method and apparatus for executing an instruction. A method may include: acquiring an instruction queue; acquiring a to-be-sent instruction from the instruction queue in preset order, and executing following sending: determining a type of the to-be-sent instruction; determining, in response to determining that the to-be-sent instruction is an arithmetic instruction, an executing component executing the to-be-sent instruction from an executing component set, and sending the to-be-sent instruction to the determined executing component; and acquiring, in response to determining that the to-be-sent instruction is a blocking instruction, a next to-be-sent instruction after receiving a signal for instructing an instruction associated with the to-be-sent instruction being completely executed.

公开(公告)号：US10189426B2

公开(公告)日：2019-01-29

申请号：US15411061

申请日：2017-01-20

Applicant: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.

Inventor： Zhao Zhang ,  Jian Ouyang ,  Jing Wang ,  Peng Wu ,  Liang Gao ,  Yupeng Li

IPC: G06F1/08 ,  G05D1/00 ,  G06F1/32 ,  B60L11/18 ,  B60R16/023

Abstract: The present application discloses a method and apparatus for operating a field-programmable gate array (FPGA) board in a driverless vehicle. The method according to a specific embodiment includes: collecting driving scenario information on a driving scenario of the driverless vehicle; determining, based on the driving scenario information, a speed at which the driverless vehicle executes a computing operation in the driving scenario; comparing the speed with a speed threshold; switching a working mode of the FPGA board in the driverless vehicle executing the computing operation to reduce power consumption of the FPGA board, in response to the speed being lower than the speed threshold. This embodiment implements the adaptive adjustment of the working mode of the FPGA board, thereby reducing the overall power consumption.