公开(公告)号：US20210287900A1

公开(公告)日：2021-09-16

申请号：US16817378

申请日：2020-03-12

Applicant: Applied Materials, Inc.

Inventor： Yixiong YANG ,  Wei LIU ,  Yuan-hui LO ,  Srinivas GANDIKOTA ,  Jacqueline Samantha WRENCH ,  Yongjing LIN ,  Wen Ting CHEN ,  ShihChung CHEN

IPC: H01L21/02

Abstract: The present disclosure provides methods for treating film layers in a substrate including positioning the substrate in a processing volume of a processing chamber. The substrate can have high aspect ratio features extending a depth from a substrate surface to a bottom surface. The feature can have a width defined by a first sidewall and a second sidewall. A film with a composition that includes metal is formed on the substrate surface and the first sidewall, the second sidewall, and the bottom surface of each feature. The film in the feature can have a seam extending substantially parallel to the first and second sidewalls. The film is annealed and exposed to an oxygen radical while converting the metal of the film to a metal oxide. The metal oxide is exposed to a hydrogen radical while converting the metal oxide to a metal fill layer.

公开(公告)号：US20220093749A1

公开(公告)日：2022-03-24

申请号：US17457597

申请日：2021-12-03

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Xuebin LI ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Tushar Vidyadhar MANDREKAR ,  Yuan-hui LO ,  Patricia M. LIU ,  Sanjay NATARAJAN ,  Saurabh CHOPRA

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.