公开(公告)号：US20220093749A1

公开(公告)日：2022-03-24

申请号：US17457597

申请日：2021-12-03

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Xuebin LI ,  Abhishek DUBE ,  Yi-Chiau HUANG ,  Tushar Vidyadhar MANDREKAR ,  Yuan-hui LO ,  Patricia M. LIU ,  Sanjay NATARAJAN ,  Saurabh CHOPRA

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/02 ,  H01L29/08 ,  H01L21/67 ,  H01L29/66

Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.