公开(公告)号：US20240275391A1

公开(公告)日：2024-08-15

申请号：US18110246

申请日：2023-02-15

Applicant: Apple Inc.

Inventor： Christian Venerus ,  Utku Seckin ,  Vikram Magoon

IPC: H03L7/093 ,  H04L27/20

CPC classification number: H03L7/093 ,  H04L27/2082

Abstract: This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.

公开(公告)号：US12212326B2

公开(公告)日：2025-01-28

申请号：US18110246

申请日：2023-02-15

Applicant: Apple Inc.

Inventor： Christian Venerus ,  Utku Seckin ,  Vikram Magoon

IPC: H03L7/093 ,  H04L27/20

Abstract: This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.

公开(公告)号：US20230378988A1

公开(公告)日：2023-11-23

申请号：US17749987

申请日：2022-05-20

Applicant: Apple Inc.

Inventor： Linxiao Zhang ,  Utku Seckin ,  Vikram Magoon

IPC: H04B1/18

CPC classification number: H04B1/18

Abstract: This disclosure is directed to a radio frequency front end circuit with improved receiver. The radio frequency front end circuit may include one or more antennas coupled directly to a mixer of the receiver. The mixer may include sampling circuitry to provide sampled signals based on receiving received signals from the one or more antennas. For example, the mixer may provide the sampled signals to a low noise amplifier (LNA) or other downstream components for further processing and/or conditioning. In some cases, the sampling circuitry may include a number of sampling circuits each sampling a portion of a received signal. Moreover, in specific cases, each of the sampling circuits may couple to an impedance matching circuit based on an impedance of the one or more antennas. The mixer may also include various filtering circuits.