公开(公告)号：US11481224B2

公开(公告)日：2022-10-25

申请号：US16557357

申请日：2019-08-30

Applicant: Apple Inc.

Inventor： Tao Mai ,  Robert G. Lorenz ,  Joachim S. Hammerschmidt ,  Utku Seckin

IPC: G06F9/38 ,  G06F9/30 ,  G06F17/16 ,  G06F1/08 ,  H03H17/02 ,  H03H17/06

Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

公开(公告)号：US20210064380A1

公开(公告)日：2021-03-04

申请号：US16557357

申请日：2019-08-30

Applicant: Apple Inc.

Inventor： Tao Mai ,  Robert G. Lorenz ,  Joachim S. Hammerschmidt ,  Utku Seckin

IPC: G06F9/38 ,  G06F9/30 ,  G06F1/08 ,  G06F17/16

Abstract: A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

公开(公告)号：US10511323B1

公开(公告)日：2019-12-17

申请号：US16143447

申请日：2018-09-26

Applicant: Apple Inc.

Inventor： Tao Mai ,  Simone Gambini

IPC: H03M1/06 ,  H03M3/00

Abstract: An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.