公开(公告)号：US20240283436A1

公开(公告)日：2024-08-22

申请号：US18647865

申请日：2024-04-26

Applicant: Apple Inc.

Inventor： Vishal Varma ,  Dhaval H. Shah ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Sumeet Gupta

IPC: H03K5/08 ,  H04L25/06

CPC classification number: H03K5/082 ,  H04L25/062

Abstract: A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.

公开(公告)号：US12028075B2

公开(公告)日：2024-07-02

申请号：US17823952

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Vishal Varma ,  Dhaval H. Shah ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Sumeet Gupta

IPC: H03K5/08 ,  H04L25/06

CPC classification number: H03K5/082 ,  H04L25/062

Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison of a reference voltage to the magnitude of signals received via a communication link that encodes a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a signal present indicator indicating the presence of data on the communication link. Once the signal present indicator is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.

公开(公告)号：US20230387898A1

公开(公告)日：2023-11-30

申请号：US17823952

申请日：2022-08-31

Applicant: Apple Inc.

Inventor： Vishal Varma ,  Dhaval H. Shah ,  Jose A. Tierno ,  Sanjeev K. Maheshwari ,  Sumeet Gupta

IPC: H03K5/08 ,  H04L25/06

CPC classification number: H03K5/082 ,  H04L25/062

Abstract: A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.