公开(公告)号：US20160055833A1

公开(公告)日：2016-02-25

申请号：US14463271

申请日：2014-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Michael A. Geary ,  Robert Kenney

IPC: G09G5/399

CPC classification number: G09G5/399 ,  G06T1/60 ,  G09G5/393 ,  G09G2330/021

Abstract: Embodiments of a unified shading controller are disclosed. The embodiments may provide a first functional unit configured to send a write request to a second functional unit. The write request may include data and the data may include one or more control bits. Upon receiving the write request, the second functional unit may check the one or more control bits, and hold the data in a given queue dependent upon the control bits.

Abstract translation: 公开了统一阴影控制器的实施例。 实施例可以提供被配置为向第二功能单元发送写入请求的第一功能单元。 写请求可以包括数据，并且数据可以包括一个或多个控制位。 在接收到写请求时，第二功能单元可以检查一个或多个控制位，并且根据控制位保持给定队列中的数据。

公开(公告)号：US09633409B2

公开(公告)日：2017-04-25

申请号：US13975520

申请日：2013-08-26

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Brian K. Reynolds ,  Michael A. Geary

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3867 ,  G06F9/3877

Abstract: Techniques are disclosed relating to predication. In one embodiment, a graphics processing unit is disclosed that includes a first set of architecturally-defined registers configured to store predication information. The graphics processing unit further includes a second set of registers configured to mirror the first set of registers and an execution pipeline configured to discontinue execution of an instruction sequence based on predication information in the second set of registers. In one embodiment, the second set of registers includes one or more registers proximal to an output of the execution pipeline. In some embodiments, the execution pipeline writes back a predicate value determined for a predicate writer to the second set of registers. The first set of architecturally-defined registers is then updated with the predicate value written back to the second set of registers. In some embodiments, the execution pipeline discontinues execution of the instruction sequence without stalling.

公开(公告)号：US20150054837A1

公开(公告)日：2015-02-26

申请号：US13975520

申请日：2013-08-26

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Brian K. Reynolds ,  Michael A. Geary

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/30072 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3867 ,  G06F9/3877

Abstract: Techniques are disclosed relating to predication. In one embodiment, a graphics processing unit is disclosed that includes a first set of architecturally-defined registers configured to store predication information. The graphics processing unit further includes a second set of registers configured to mirror the first set of registers and an execution pipeline configured to discontinue execution of an instruction sequence based on predication information in the second set of registers. In one embodiment, the second set of registers includes one or more registers proximal to an output of the execution pipeline. In some embodiments, the execution pipeline writes back a predicate value determined for a predicate writer to the second set of registers. The first set of architecturally-defined registers is then updated with the predicate value written back to the second set of registers. In some embodiments, the execution pipeline discontinues execution of the instruction sequence without stalling.

Abstract translation: 公开了与预测有关的技术。 在一个实施例中，公开了一种图形处理单元，其包括被配置为存储预测信息的第一组体系结构定义的寄存器。 图形处理单元还包括配置为镜像第一组寄存器的第二组寄存器和配置为基于第二组寄存器中的预测信息中止指令序列的执行的执行流水线。 在一个实施例中，第二组寄存器包括靠近执行流水线的输出的一个或多个寄存器。 在一些实施例中，执行流水线将为谓词写入器确定的谓词值写回到第二组寄存器。 然后，第一组体系结构定义的寄存器被更新，并将谓词值写回第二组寄存器。 在一些实施例中，执行流水线不中断执行指令序列。

公开(公告)号：US10324726B1

公开(公告)日：2019-06-18

申请号：US15429982

申请日：2017-02-10

Applicant: Apple Inc.

Inventor： Michael A. Geary ,  Brian K. Reynolds ,  Terence M. Potter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0897 ,  G06F12/0875

Abstract: Techniques are disclosed relating to scheduling graphics instructions for execution on different types of execution units based on characteristics of decoded and cached graphics instruction. In some embodiments, a graphics unit includes multiple different types of execution units that are configured to execute different types of instructions (e.g., different units for datapath, sample, load/store, etc.). In some embodiments, the graphics unit stores decoded instructions in an instruction cache in at least one cache level, along with information specifying characteristics of the instructions. The characteristics may be stored at clause granularity and may indicate the type of instructions in each clause (e.g., corresponding to which type of execution unit is configured to execute the instructions). In some embodiments, scheduling circuitry is configured to access the information and select instructions from the instruction cache to send to ones of the plurality of execution units based on the stored information.

公开(公告)号：US09437172B2

公开(公告)日：2016-09-06

申请号：US14463271

申请日：2014-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Michael A. Geary ,  Robert Kenney

IPC: G09G5/36 ,  G06T1/60 ,  G09G5/399 ,  G09G5/393

CPC classification number: G09G5/399 ,  G06T1/60 ,  G09G5/393 ,  G09G2330/021

Abstract: Embodiments of a unified shading controller are disclosed. The embodiments may provide a first functional unit configured to send a write request to a second functional unit. The write request may include data and the data may include one or more control bits. Upon receiving the write request, the second functional unit may check the one or more control bits, and hold the data in a given queue dependent upon the control bits.

Abstract translation: 公开了统一阴影控制器的实施例。 实施例可以提供被配置为向第二功能单元发送写入请求的第一功能单元。 写请求可以包括数据，并且数据可以包括一个或多个控制位。 在接收到写请求时，第二功能单元可以检查一个或多个控制位，并且根据控制位保持给定队列中的数据。