公开(公告)号：US20180217659A1

公开(公告)日：2018-08-02

申请号：US15935274

申请日：2018-03-26

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, JR. ,  Richard F. Russo

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3293 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5044 ,  G06F9/5094 ,  G06F2009/45579 ,  Y02D10/122 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

公开(公告)号：US20170068575A1

公开(公告)日：2017-03-09

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, JR. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。