公开(公告)号：US20250094565A1

公开(公告)日：2025-03-20

申请号：US18790895

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier

IPC: G06F21/53 ,  G06F21/62

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes user interface and user interface pipeline circuitry coupled to the user interface. The user interface pipeline circuitry is configured to process a set of data received from a first source to produce an output for the user interface of the computing device, receive, from a second source, an indication that a component of the computing device has been activated, and, prior to presenting the output via the user interface, insert, into the output, an indicator of the component being activated.

公开(公告)号：US20250094564A1

公开(公告)日：2025-03-20

申请号：US18790765

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier

IPC: G06F21/53 ,  G06F21/62

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes a sensor and sensor processor circuitry coupled to the sensor. The sensor processor circuitry is configured to process sensor data received from a sensor of the computing device. In response to a first indication that a first consumer is trustworthy, the sensor processor circuitry is configured to provide a first data set of the processed sensor data to the first consumer. In response to a second indication that a second consumer is untrustworthy, the sensor processor circuitry is configured to negotiate one or more conditions in which the second consumer is permitted to receive a second data set of the processed sensor data.

公开(公告)号：US20230394276A1

公开(公告)日：2023-12-07

申请号：US17833476

申请日：2022-06-06

Applicant: Apple Inc.

Inventor： Sayyed Karen Khatamifard ,  Chenfan Sun ,  Alon Yaakov ,  Husam Khashiboun ,  Jeffrey D. Marker ,  Saman Naderiparizi ,  Ramana V. Rachakonda ,  Rohit K. Gupta

IPC: G06N3/04 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06N3/04 ,  G06F9/4881 ,  G06F9/5016

Abstract: Embodiments relate to streaming convolution operations in a neural processor circuit that includes a neural engine circuit and a neural task manager. The neural task manager obtains multiple task descriptors and multiple subtask descriptors. Each task descriptor identifies a respective set of the convolution operations of a respective layer of a set of layers. Each subtask descriptor identifies a corresponding task descriptor and a subset of the convolution operations on a portion of a layer of the set of layers identified by the corresponding task descriptor. The neural processor circuit configures the neural engine circuit for execution of the subset of the convolution operations using the corresponding task descriptor. The neural engine circuit performs the subset of the convolution operations to generate output data that correspond to input data of another subset of the convolution operations identified by another subtask descriptor from the list of subtask descriptors.

公开(公告)号：US20250094563A1

公开(公告)日：2025-03-20

申请号：US18790529

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier ,  Kenneth W. Waters

IPC: G06F21/53 ,  G06F21/54

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes one or more processors configured to co-execute trusted processes and untrusted processes in an isolated manner that includes implementing a secure environment in which a set of security criteria is enforced for data of the trusted processes. The computing device further includes multiple heterogenous hardware accelerators configured to implement exclaves of the secure environment that extend enforcement of one or more of the set of security criteria within the hardware accelerators for data distributed to the hardware accelerators for performance of tasks associated with the trusted processes.

公开(公告)号：US20230368008A1

公开(公告)日：2023-11-16

申请号：US17745032

申请日：2022-05-16

Applicant: Apple Inc.

Inventor： Sayyed Karen Khatamifard ,  Alexander J. Kirchhoff ,  Rohit K. Gupta ,  Jeffrey D. Marker ,  Thomas G. Anderl ,  Saman Naderiparizi ,  Chenfan Sun ,  Alon Yaakov ,  Husam Khashiboun ,  Ramana V. Rachakonda

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.