-
公开(公告)号：US10128859B1
公开(公告)日：2018-11-13
申请号：US15899883
申请日：2018-02-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Sanjay Rajasekhar , Roberto Sergio Matteo Maurino
Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.
-
公开(公告)号：US20150270805A1
公开(公告)日：2015-09-24
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
-
Patent Agency Ranking
公开(公告)号：US10409312B1
公开(公告)日：2019-09-10
申请号：US16040207
申请日：2018-07-19
Applicant: Analog Devices Global Unlimited Company
Inventor： Sanjay Rajasekhar
Abstract: A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.
-
公开(公告)号：US09294037B2
公开(公告)日：2016-03-22
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
-
公开(公告)号：US20180167067A1
公开(公告)日：2018-06-14
申请号：US15375906
申请日：2016-12-12
Applicant: Analog Devices Global
Inventor： Christopher Peter Hurrell , Sanjay Rajasekhar
IPC: H03K17/693 , H02J7/00
CPC classification number: H02J7/0013 , H02J7/345 , H03K17/005 , H03K17/0416 , H03K17/693
Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.
-
公开(公告)号：US09800262B1
公开(公告)日：2017-10-24
申请号：US15258910
申请日：2016-09-07
Applicant: Analog Devices Global
Inventor： Roberto Sergio Matteo Maurino , Sanjay Rajasekhar , Pasquale Delizia , Colin G. Lyden , Gabriel Banarie
Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.
-
公开(公告)号：US09391628B1
公开(公告)日：2016-07-12
申请号：US14967880
申请日：2015-12-14
Applicant: ANALOG DEVICES GLOBAL
Inventor： Colin G. Lyden , Pasquale Delizia , Sanjay Rajasekhar , Yogesh Jayarman Sharma , Arthur J. Kalb , Marvin L. Shu , Gerard Mora-Puchalt , Roberto S. Maurino
CPC classification number: H03M1/1245 , G11C27/026
Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.
Abstract translation: 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。
-
-
-
-
-
-
Search Results
7
records
(took 0.012 seconds)
