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公开(公告)号：US20170207907A1
公开(公告)日：2017-07-20
申请号：US15336414
申请日：2016-10-27
Applicant: Analog Devices Global
Inventor： Mayur Gurunath Anvekar , Venkata Aruna Srikanth Nittala , Roberto Sergio Matteo Maurino , Naiqian Ren
CPC classification number: H04L7/0331 , G01S7/521 , H04L7/0012 , H04L7/0029 , H04L41/0896
Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.
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公开(公告)号：US09941897B1
公开(公告)日：2018-04-10
申请号：US15692812
申请日：2017-08-31
Applicant: Analog Devices Global
Inventor： Hongxing Li , Roberto Sergio Matteo Maurino
CPC classification number: H03M1/201 , H03M1/0639 , H03M1/0673 , H03M1/462 , H03M1/66 , H03M1/68 , H03M3/33 , H03M3/42 , H03M3/50
Abstract: A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.
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公开(公告)号：US10312926B2
公开(公告)日：2019-06-04
申请号：US16013425
申请日：2018-06-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Roberto Sergio Matteo Maurino
Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
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公开(公告)号：US20190131989A1
公开(公告)日：2019-05-02
申请号：US16013425
申请日：2018-06-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Roberto Sergio Matteo Maurino
IPC: H03M1/08
Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power.Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.
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Patent Agency Ranking
公开(公告)号：US10211788B2
公开(公告)日：2019-02-19
申请号：US15445389
申请日：2017-02-28
Applicant: Analog Devices Global
Inventor： Roderick McLachlan , Roberto Sergio Matteo Maurino
Abstract: A converter circuit is provided that includes an amplifier circuit and further includes: a summing current resistor that exhibits nonlinear resistance coupled between a voltage node and a summing current node of the amplifier; a compensation resistor circuit includes resistors that exhibit nonlinear resistance; the compensation resistor circuit produces a compensation current at the summing current node that compensates for nonlinear current flow in the summing current resistor.
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公开(公告)号：US10128859B1
公开(公告)日：2018-11-13
申请号：US15899883
申请日：2018-02-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Sanjay Rajasekhar , Roberto Sergio Matteo Maurino
Abstract: Techniques are described to cancel kT/C sampling noise and residue amplifier sampling noise while also reducing power consumption in a pipelined analog-to-digital converter circuit.
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公开(公告)号：US09893877B2
公开(公告)日：2018-02-13
申请号：US15336414
申请日：2016-10-27
Applicant: Analog Devices Global
Inventor： Mayur Gurunath Anvekar , Venkata Aruna Srikanth Nittala , Roberto Sergio Matteo Maurino , Naiqian Ren
CPC classification number: H04L7/0331 , G01S7/521 , H04L7/0012 , H04L7/0029 , H04L41/0896
Abstract: Techniques for synchronization between multiple sampling circuits using a single pin interface to control an output data rate are described. The frequency or rate of a signal on this pin can be automatically determined and used to accomplish the required output data rate. Also described are techniques for using a single pin interface that can allow a sampling device to operate either in a master mode that can generate data strobes, or in a slave mode that can receive a convert start signal. Also described are techniques for controlling bandwidth and throughput for individual channels in a multi-channel device using a single pin interface. For example, using various techniques of this disclosure, integer multiple rate control for other channels can be provided thereby providing varying ODR for different channels, which can also control the bandwidth of interest.
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公开(公告)号：US20180248527A1
公开(公告)日：2018-08-30
申请号：US15445389
申请日：2017-02-28
Applicant: Analog Devices Global
Inventor： Roderick McLachlan , Roberto Sergio Matteo Maurino
IPC: H03F3/45
CPC classification number: H03F1/32 , G05F1/561 , H03F1/3211 , H03F3/45475 , H03F2203/45528
Abstract: A converter circuit is provided that includes an amplifier circuit and further includes: a summing current resistor that exhibits nonlinear resistance coupled between a voltage node and a summing current node of the amplifier; a compensation resistor circuit includes resistors that exhibit nonlinear resistance; the compensation resistor circuit produces a compensation current at the summing current node that compensates for nonlinear current flow in the summing current resistor.
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公开(公告)号：US09800262B1
公开(公告)日：2017-10-24
申请号：US15258910
申请日：2016-09-07
Applicant: Analog Devices Global
Inventor： Roberto Sergio Matteo Maurino , Sanjay Rajasekhar , Pasquale Delizia , Colin G. Lyden , Gabriel Banarie
Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.
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