-
公开(公告)号：US11144324B2
公开(公告)日：2021-10-12
申请号：US16586642
申请日：2019-09-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
-
公开(公告)号：US12204911B2
公开(公告)日：2025-01-21
申请号：US17497572
申请日：2021-10-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
-
Patent Agency Ranking
公开(公告)号：US20210096874A1
公开(公告)日：2021-04-01
申请号：US16586642
申请日：2019-09-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
-
公开(公告)号：US20210157598A1
公开(公告)日：2021-05-27
申请号：US16697147
申请日：2019-11-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Neil N. Marketkar , Arun A. Nair
Abstract: Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.
-
公开(公告)号：US12190117B2
公开(公告)日：2025-01-07
申请号：US16697147
申请日：2019-11-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Neil N. Marketkar , Arun A. Nair
Abstract: Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.
-
公开(公告)号：US11977890B2
公开(公告)日：2024-05-07
申请号：US17566040
申请日：2021-12-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Magiting M. Talisayon , Luca Schiano , Neil N. Marketkar , Yueh-Chuan Tzeng
CPC classification number: G06F9/30149 , G06F9/30058 , G06F9/30065 , G06F9/3836 , G06F9/3861
Abstract: Stateful microbranch instructions, including: generating, based on an instruction, a first one or more microinstructions including a stateful microbranch instruction, wherein the stateful microbranch instruction includes: an address of a next instruction after the instruction; a branch target address; one or more microcode attributes; and executing the first one or more microinstructions.
-
公开(公告)号：US20220027162A1
公开(公告)日：2022-01-27
申请号：US17497572
申请日：2021-10-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthew T. Sobel , Joshua James Lindner , Neil N. Marketkar , Kai Troester , Emil Talpes , Ashok Tirupathy Venkatachar
IPC: G06F9/38
Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
-
-
-
-
-
-
Search Results
7
records
(took 0.038 seconds)
