公开(公告)号：US11144324B2

公开(公告)日：2021-10-12

申请号：US16586642

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

公开(公告)号：US12204911B2

公开(公告)日：2025-01-21

申请号：US17497572

申请日：2021-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

公开(公告)号：US20220027162A1

公开(公告)日：2022-01-27

申请号：US17497572

申请日：2021-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

公开(公告)号：US20210096874A1

公开(公告)日：2021-04-01

申请号：US16586642

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.