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    MEMORY ACCESS RESPONSE MERGING IN A MEMORY HIERARCHY
    1.
    发明申请
    MEMORY ACCESS RESPONSE MERGING IN A MEMORY HIERARCHY 有权

    公开(公告)号：US20220091980A1

    公开(公告)日：2022-03-24

    申请号：US17031706

    申请日：2020-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Onur Kayiran ,  Yasuko Eckert ,  Mark Henry Oskin ,  Gabriel H. Loh ,  Steven E. Raasch ,  Maxim V. Kazakov

    IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0877 ,  G06F13/16 ,  G06F11/30

    Abstract: A system and method for efficiently processing memory requests are described. A computing system includes multiple compute units, multiple caches of a memory hierarchy and a communication fabric. A compute unit generates a memory access request that misses in a higher level cache, which sends a miss request to a lower level shared cache. During servicing of the miss request, the lower level cache merges identification information of multiple memory access requests targeting a same cache line from multiple compute units into a merged memory access response. The lower level shared cache continues to insert information into the merged memory access response until the lower level shared cache is ready to issue the merged memory access response. An intermediate router in the communication fabric broadcasts the merged memory access response into multiple memory access responses to send to corresponding compute units.

    TECHNIQUES FOR CHANGING MANAGEMENT MODES OF MULTILEVEL MEMORY HIERARCHY
    2.
    发明申请
    TECHNIQUES FOR CHANGING MANAGEMENT MODES OF MULTILEVEL MEMORY HIERARCHY 审中-公开
    改变多层次记忆层次管理模式的技术

    公开(公告)号：US20160179382A1

    公开(公告)日：2016-06-23

    申请号：US14576912

    申请日：2014-12-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sergey Blagodurov ,  Mitesh Ramesh Meswani ,  Gabriel H. Loh ,  Mauricio Breternitz, JR. ,  Mark Richard Nutter ,  John Robert Slice ,  David Andrew Roberts ,  Michael Ignatowski ,  Mark Henry Oskin

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/0685

    Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g.,. computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.

    Abstract translation: 处理器基于在处理器上执行的应用的应用阶段的变化来修改多层存储器层级的一系列存储器位置的存储器管理模式。 处理器监视执行应用程序的应用阶段（例如，计算限制阶段，输入/输出阶段或存储器访问阶段）并且响应于阶段的改变来咨询管理策略以识别存储器管理模式。 处理器自动重新配置存储器控制器和其他模块，使得根据所识别的存储器管理模式来管理多级存储器层级的一系列存储器位置。 通过根据应用阶段改变存储器位置范围的存储器管理模式，处理器提高了处理效率和灵活性。

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