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公开(公告)号：US20220269640A1
公开(公告)日：2022-08-25
申请号：US17668512
申请日：2022-02-10
Applicant: Apple Inc.
Inventor： Ian P. Shaeffer , Eric C. Gaertner , John T. Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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公开(公告)号：US20200311012A1
公开(公告)日：2020-10-01
申请号：US16815239
申请日：2020-03-11
Applicant: Apple Inc.
Inventor： Ian P. Schaeffer , Eric C. Gaertner , John T. Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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公开(公告)号：US20240396731A1
公开(公告)日：2024-11-28
申请号：US18670151
申请日：2024-05-21
Applicant: Apple Inc.
Inventor： Paul A. Baker , Michael W. Murphy , Mark P. Colosky , James E. Zmuda , Jangwon Lee , Kevin C. Gotze , Peter Louis Bielawski
IPC: H04L9/32
Abstract: Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.
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公开(公告)号：US11726835B2
公开(公告)日：2023-08-15
申请号：US16872685
申请日：2020-05-12
Applicant: Apple Inc.
Inventor： Michael W. Murphy , Gopal Thirumalai Narayanan , Deepak K. Mishra , Andre M. Glover , Sreenivas Tallam , Hardik K. Doshi
IPC: G06F9/50 , G06F13/42 , G06F13/40 , H04L47/125
CPC classification number: G06F9/5083 , G06F9/505 , G06F13/4022 , G06F13/4027 , G06F13/4221 , G06F13/4282 , H04L47/125 , G06F2213/0024 , G06F2213/0026
Abstract: A method and apparatus of a device that load balances a first plurality of Peripheral Connect Interconnect ports is described. In an exemplary embodiment, the device detects a second plurality of PCI ports in the device. In addition, the device determines a load for each port in the first and second plurality of PCI ports and sorts the second plurality of PCI ports. The device further load balances the first plurality of PCI ports using at least a PCIe switch and the load determination of the second plurality of PCI ports. The device additionally communicates data between the first and second plurality of PCI ports.
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公开(公告)号：US11281619B2
公开(公告)日：2022-03-22
申请号：US16815239
申请日：2020-03-11
Applicant: Apple Inc.
Inventor： Ian P. Schaeffer , Eric C. Gaertner , John T. Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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Patent Agency Ranking
公开(公告)号：US20140082242A1
公开(公告)日：2014-03-20
申请号：US13622266
申请日：2012-09-18
Applicant: APPLE INC.
Inventor： Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
IPC: G06F13/24
CPC classification number: G06F13/24 , G06F1/3253 , Y02D10/151
Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。
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公开(公告)号：US20150227476A1
公开(公告)日：2015-08-13
申请号：US14691244
申请日：2015-04-20
Applicant: Apple Inc.
Inventor： Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
CPC classification number: G06F13/24 , G06F1/3253 , Y02D10/151
Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。
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公开(公告)号：US12015710B2
公开(公告)日：2024-06-18
申请号：US17374456
申请日：2021-07-13
Applicant: Apple Inc.
Inventor： Paul A. Baker , Michael W. Murphy , Mark P. Colosky , James E. Zmuda , Jangwon Lee , Kevin C. Gotze , Peter Louis Bielawski
IPC: H04L9/32
CPC classification number: H04L9/32
Abstract: Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.
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公开(公告)号：US11741041B2
公开(公告)日：2023-08-29
申请号：US17668512
申请日：2022-02-10
Applicant: Apple Inc.
Inventor： Ian P. Shaeffer , Eric C. Gaertner , John T Orchard , Michael W. Murphy , Ronald P. Songco , Corey N. Axelowitz , Brett W. Degner
CPC classification number: G06F13/4282 , H01R12/737 , H01R13/6683 , G06F2213/0026 , H01R2201/06
Abstract: A computer includes a processor, a PCIe-compatible interface bus that includes a root that is connected to the processor, and a routing complex that is connected to the root and is controlled by the processor. The computer also includes a first interface slot that is connectable to the root by the switches, a second interface slot that is connectable to the root by the switches, and an extended interface slot that is connectable to the root by the switches. The switches are configured based on properties of a first peripheral device to define a first switching configuration when the first peripheral device is connected only to the first interface slot and to define a second switching configuration when the first peripheral device is connected to both of the first interface slot and the extended interface slot.
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公开(公告)号：US20230019372A1
公开(公告)日：2023-01-19
申请号：US17374456
申请日：2021-07-13
Applicant: Apple Inc.
Inventor： Paul A. Baker , Michael W. Murphy , Mark P. Colosky , James E. Zmuda , Jangwon Lee , Kevin C. Gotze , Peter Louis Bielawski
Abstract: Various techniques related to authenticating and verifying the integrity of data received by a computer system from an external source (such as a sensor) are disclosed. Hardware circuits are disclosed that, along with the computer processor, allow for error-checking and authentication of data received by the computer system. For instance, the hardware circuits may generate a separate authentication code that can be compared to the authentication code in the data itself to determine whether or not the message is authentic and whether or not there is an error in the data. The disclosed techniques reduce the processing requirements of a computer system and can be implemented using simple hardware circuit designs.
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